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Visitor
Visitor
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Registered: ‎07-23-2020

[Common 17-55] 'set_property' expects at least one object. ["C:/Users/Public/svn_wa/branches/FPGA/FPGA_GEN_Merge/source/Generator_timing.xdc":21] Spartan 6 to Spartan 7

 I am having some difficulty transitioning from a Spartan 6 FPGA board over to a Spartan 7 FPGA board through Xilinx. I have reached out through the forums several times, but in general am not receiving the assistance I need. Namely, one issue I am running into during the implementation build in Vivado is the critical warning:

[Common 17-55] 'set_property' expects at least one object. ["C:/Users/Public/svn_wa/branches/FPGA/FPGA_GEN_Merge/source/Generator_timing.xdc":21]


I have created the XDC file, and received verification that it is being set up properly, as well as assigned all of the pins to their new FPGA schematic. I am not sure what the object refers to in the warning message, or why the set_property lines appear empty. Below is an example of the lines I use in the XDC, as well as the prior UCF counterpart:

UCF: NET "Tripped_Wire" LOC = "C7" | IOSTANDARD = LVCMOS33;
XDC: set_property PACKAGE_PIN C7 [get_ports {Tripped_Wire}]
          set_property IOSTANDARD LVCMOS33 [get_ports {Tripped_Wire}]

Some specific questions I would like to address:

Does this warning typically point to a deeper issue?

What exactly is the "object" referred to in the critical warning? Is this one part of the set_property line? Or is this referential to something completely separate? 

Is there another header that I could use instead of "set_property" that might work better? 

Is it appropriate to use "get_ports" to assign pins in the schematic? Or is there a "get_pins" or another header to use that would work better?

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Teacher
Teacher
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Registered: ‎10-23-2018

@Erin 

This might not be the same issue, but maybe it will give some insight.. https://www.xilinx.com/support/answers/56169.html

Hope that helps. If so, please mark as solution accepted. Kudos also welcomed

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Registered: ‎01-22-2015

@Erin 

I am sorry that we did not solve this problem during our previous discussions.

In short, the following constraints (that you show) are formatted correctly:

set_property PACKAGE_PIN C7 [get_ports {Tripped_Wire}]
set_property IOSTANDARD LVCMOS33 [get_ports {Tripped_Wire}]

The error you are getting specifically refers to the port name, Tripped_Wire.

The error usually means that Tripped_Wire does not match a port name in the top-level component of your Vivado project.  This "not matching" means that there is either a spelling error or the cases of the letters do not match (ie. port names are case sensitive).

Since you are getting this error often, it sounds like Vivado is not recognizing your top-level component.  Can you check this?

Anyway, no need for you to struggle with this anymore.  Can you archive your Vivado project (File > Project > Archive...) and attached it to your next post?   I will find the problem for you.

Cheers,
Mark

 

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Visitor
Visitor
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Registered: ‎07-23-2020

Thank you for the response. I am not able to attach my project due to confidentiality issues, but I was able to figure out the issue, at least in regards to this .xdc file. I was reading some of the user guides, and noticed that 'set_property' was general constraint, but that there were more specific tags for physical constraints. I changed all of the 'set_property' tags to 'set_package_pin_val,' and that seemed to resolve the critical warning. I will be posting another forum question with another issue, but for now this is resolved. Thank you again for the assistance

Vivado_XDC_constraint_tags.PNG
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Guide
Guide
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Registered: ‎01-23-2009

The set_package_pin_val command is not a replacement for "set_property PACKAGE_PIN ...". In fact, I am not even sure what the set_package_pin_val command is used for...

Looking at some of your more recent posts, it looks like you have a bit of a problem. While the task you have been asked to do may have been presented as "converting a design from Spartan-6 to Spartan-7", this is a much more complex task. Fundamentally, ISE (which must be used for Spartan-6) and Vivado (which must be used for Spartan-7) are completely different tools and (other than the actual RTL) use completely different inputs. The entire design flow is different, and, as you are seeing, the constraint system is completely different.

As a result, what you are really being asked to do is "Implement an existing RTL design in Vivado". You can't just do this blind - you need to understand the process flow and the constraint system, and a bit of "generally what is going on". Asking individual questions on the Xilinx forums isn't going to get you there...

My suggestion is you look at some of the Xilinx classes - specifically the "Designing FPGAs Using the Vivado Design Suite" series of course. Taking even the first two (out of four) will go a long way toward giving you enough knowledge to do what you are trying to do. These classes are available as on-demand e-learning and aren't that expensive...

Avrum

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Visitor
Visitor
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Registered: ‎07-23-2020

I did not replace set_property PACKAGE_PIN with set_package_pin_val, rather, I just replaced set_property.

From:
set_property PACKAGE_PIN G2 [get_pins FAULT]
To:
set_package_pin_val PACKAGE_PIN G2 [get_pins FAULT]

I went back and reverted the changes I made to see if it would work after some other minor changes had been made, and the critical warning reappeared, which leads me to believe that the set_package_pin_val effectively solved this warning.

Thank you for your advice. I went ahead and found a few background videos to give me some basic understanding, and although I had come in contact with much of what was covered, the review was more than helpful.

I was able to finally resolve the implementation build failure, which came after I implemented the timing.xdc, as well as set main.v as the top module (the application's reflexive choice was a test bench, and did not include all necessary information) I am now moving onto the generate bitstream errors, of which I sure there will be a few, so I look forward to receiving your help in the future.
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Guide
Guide
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Registered: ‎01-23-2009

set_package_pin_val PACKAGE_PIN G2 [get_pins FAULT]

This does not set the PACKAGE_PIN. This command has something to do with setting up a specific graphical view, but does not affect placement. You will find that after implementation, any pins you think you set this way will end up being unplaced (or actually randomly assigned by the tool) - you will not be able to generate a bitstream with this.

I don't know what problem you think you are fixing with this command, but you are merely masking it, not solving it.

Avrum