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Angel_fito17
Participant
Participant
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Registered: ‎03-23-2020

Communicate PS and PL frequencies

Hi, I am doing a communication between PS and PL writing in an address with BRAM, its work correctly, I wrote a program in PL side which write a counter and I read in PS with SDK, but I have a question. I write in FPGA with a clock of 125MHz, and the clock of the arm is the 666MHz. How can this work correctly, the system take the clock of lower rate?Don't I need configurate the frequencies? Thanks in advance

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dgisselq
Scholar
Scholar
242 Views
Registered: ‎05-21-2015

@Angel_fito17,

The answer is that it requires extensive use of some asynchronous FIFOs.  You can find a discussion of what an asynchronous FIFO is and how it works here.  You can also find a rough (open source) AXI implementation that can cross clock domains using an asynchronous FIFO here.  The fact is, given the way AXI is structured, this cross-clock domain approach actually works fairly easily.

Dan

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