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Observer
Observer
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Registered: ‎06-14-2018

Configurable phase shifter

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Hi,

I'm trying to build a configurable phase shifter, with the below inputs:

input wire reset
input wire clk,  //fast clock for phase shifting 100Mhz
input wire [6:0] del, //number of delays
input wire clk_in,  // the clock to be shifted 
output wire clk_out // the output clock

 

I've tried use the MMCM but it is not dynamic and hard to support 100Mhz clocks.
If it's possible to supply an example for that with the below parameters:

clk = 100Mhz

clk_in = 25Mhz (divided clock by 4 of the clk)

del = 1 (shifting the output clock in 10ns -> one cycle of clock)

clk_out = 25Mhz clock shifted by 10ns from the clk_in

 

Thanks,
Neta

 

 

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Highlighted
Observer
Observer
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Registered: ‎06-14-2018

Hi,
Thanks for the support.
This clock is needed for internal logic in the FPGA of sampling an analog signal from the interface.
So there is a need to control all the phases.
That's it, this is not going to be an output of the FPGA.

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Guide
Guide
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Registered: ‎01-23-2009

I'm not sure what you are trying to accomplish here.

Let me first address your comments on the MMCM. You say that the MMCM is "not dynamic" - this isn't correct. The MMCM specifically has a Dynamic Fine Phase Shift which can dynamically change the phase of the clock in increments of 1 / 56*fVCO where fVCO is the VCO frequency, which is a multiplied version of your CLK_IN, usually between 1200MHz and 1600MHz. See UG472 (for 7 series) in the MMCM section "Dynamic Phase Shift Interface in the MMCM".

However, it appears that you aren't really looking at fine phase shifting, more about shifting a 25MHz clock in increments of 1/4 of the clock period. Since the FPGA can easily run at 100MHz, you can design this functionally; it needs a counter running at 100MHz that counts from 0 to 3; changing the "phase" of the clock merely means changing which counts of the counter represent the high time vs. the low time (or at least where the 0-1 transition of this output is).

Depending on what you want to do with this clock, the mechanism for generating it can be different. If this clock is simply to go out of the FPGA (and not clock anything inside the FPGA), then just clock it out of the FPGA using an IOB flip-flop or ODDR (with an ODDR, you can even do this with a clock running at 50MHz, since you can independently control the output value on both the rising and falling edge of the internal 50MHz clock).

If you plan to use this internally (and it is hard to imagine a system that has this as a requirement), then you would have to use something like the BUFGCE or BUFHCE to determine which one of the 100MHz clock periods in a group of 4 to "enable". This clock could be used internally, as it is generated by dedicated clocking logic and routed on a dedicated clock route, but would only have a duty cycle of 5ns high and 35ns low (for your 25MHz or 40ns clock period). Take a look at this post on using the BUFGCE/BUFHCE.

But if you tell us why you need this maybe we can give you a better answer...

Avrum

 

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Observer
Observer
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Registered: ‎06-14-2018

Hi,
Thanks for the support.
This clock is needed for internal logic in the FPGA of sampling an analog signal from the interface.
So there is a need to control all the phases.
That's it, this is not going to be an output of the FPGA.

View solution in original post

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