07-14-2020 01:38 AM
In our design the Kintex FPGA fails to configure in the Master BPI mode from parallel S29GL256S10 (Cypress, former Spansion) flash. We observe the following behavior:
• The configuration is successfully written via Vivado HW manager into parallel flash. The verification and device readout of programmed configuration are successful.
• INIT_B line is released by FPGA and the flash address (line a0) is toggling.
• DONE line remains low.
• Manual pulling down of PROG_B and INIT_B line shows no effect.
See attached pdf document for more details. Thank you in advance for any hints!
07-20-2020 11:27 PM
I cannot open your attachment. First of all, read out the status register after configuration failure.
You can check your connection as well, take a REV board for a reference and see if you've connected anything wrong, such as the pullups.
07-22-2020 05:02 AM - edited 07-22-2020 05:03 AM
Apparently the attachment can't be opened directly in Chrome (or other browsers). Therefore, download it to your local drive and then open it with Adobe PDF Reader application.