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valerij.matrose
Visitor
Visitor
339 Views
Registered: ‎05-16-2019

Configuration fails in Master BPI mode

In our design the Kintex FPGA fails to configure in the Master BPI mode from parallel S29GL256S10 (Cypress, former Spansion) flash. We observe the following behavior:
• The configuration is successfully written via Vivado HW manager into parallel flash. The verification and device readout of programmed configuration are successful.
• INIT_B line is released by FPGA and the flash address (line a0) is toggling.
• DONE line remains low.
• Manual pulling down of PROG_B and INIT_B line shows no effect.

See attached pdf document for more details. Thank you in advance for any hints!

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iguo
Xilinx Employee
Xilinx Employee
241 Views
Registered: ‎08-10-2008

I cannot open your attachment. First of all, read out the status register after configuration failure.

You can check your connection as well, take a REV board for a reference and see if you've connected anything wrong, such as the pullups.

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valerij.matrose
Visitor
Visitor
218 Views
Registered: ‎05-16-2019

Dear Iguo,

Apparently the attachment can't be opened directly in Chrome (or other browsers). Therefore, download it to your local drive and then open it with Adobe PDF Reader application.

Kind regards,

Valerij

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