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elFreak
Visitor
Visitor
1,092 Views
Registered: ‎04-21-2020

Configure Zynq Ultrascale+ PL with Vivado failed

Hi

I'm trying to configure the PL of a Zynq Ultrascale+ with the Vivado Hardware Manager but I got the error message: "ERROR: [Labtools 27-3755] PL Power Status OFF, cannot program PL. Check that POR_B signal is LOW or BOOT mode is JTAG."

The Ultrascale is connected to the computer via JTAG.

So I checked all the relevent registers in the PS and all have the expected values. I checked the following registers:

CSU.JTAG_CHAIN_STATUS: 0x3 -> PL TAP is connected to the JTAG chain
CSU.JTAG_SEC: 0x3F -> PL security gate is dissabled

PMU.PWR_STATE.PL: 1 -> PL is powered on

Unfortunately, I can't set the boot mode to JTAG because the of the modul I bought. In the moment it is set to SD1 that means "0101". So I set the "alt_boot_mode" bits to "0000" and the "use_alt" to "1" in the CRL_APB.BOOT_MODE_USER register. This should change the boot mode to JTAG. However, I still couldn't configure the PL from Vivado.

Does anyone know where the problem is? As far as I know everything should be configured correctly to let Vivado configure the PL over JTAG.

Kind regards Marc

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2 Replies
shantmoses
Adventurer
Adventurer
970 Views
Registered: ‎07-01-2008

Hi,

I had the same problem with a board that can't be set to JTAG boot mode, interestingly Vitis was able to configure the PL, and once initially configured, Vivado was able to reprogram the PL afterwards.

Regards,

Shant

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wduffy
Xilinx Employee
Xilinx Employee
922 Views
Registered: ‎01-21-2013

Hi @elFreak,

 

May I ask the version of Vivado you are using? 

From 2019.2, there seems to be a change in behavior where its not possible to load the bit file and program the PL unless in JTAG mode for the MPSoC devices. 

It was possible from 2019.1 and previous versions. 

We have filed a request to have this investigated and we will soon release an AR to document the behavior. 

In the meantime, you could use JTAG mode if available to you. 

Otherwise, you could also run the below xsdb script prior to programming as a workaround:

# Set target into JTAG mode
puts "reset and setup system into JTAG mode"
targets -set -nocase -filter {name =~ "*PSU*"}
stop
after 1000
mwr  0xff5e0200 0x0100
rst -system
after 1000

 Does that help?

 

Thanks,
Wendy
Xilinx Technical Support
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