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Visitor element
Visitor
1,721 Views
Registered: ‎08-07-2017

Controlling SPI flash after configuration on Artix 7

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We have a product prototype PCB that uses the XC7A35TFGG484 Artix FPGA.

 

This design has a S25FL127 SPI flash chip for use by the Artix for configuration data and I plan to use it in multiboot mode for a backup fallback image.

 

This design has several DSPs which need to be loaded with their own firmware images, which I had thought I could store in unused areas of the same flash chip.  Additionally I had thought it might be possible to update the primary area of the flash from user logic (for in field software updates from the master controller system).

 

After researching the CCLK_0 pin though (SPI clock line to flash), I think this might be impossible with the current design though, since it seems this pin is not user controllable.  Is there any way to communicate with the SPI flash from user logic with the CCLK_0 pin?  If not, could another user I/O pin also be connected to the CCLK_0 net, in a way where it would come up tri-stated prior to configuration and not interfere with the configuration load?

 

Assuming I find a solution to access the SPI chip independently, would it be possible to program it using the FPGA after it has been configured?  I assume the FPGA does not rely on the FLASH chip after it has been configured, so I think the answer is yes.

 

Thank you for any help on this.

 

Best regards,

 

Element Green

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Accepted Solutions
Explorer
Explorer
1,646 Views
Registered: ‎06-13-2012

Re: Controlling SPI flash after configuration on Artix 7

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Hi @element,

 

if you've already a working front end and you just need to access the clk pin, instantiate the STARTUPE2

 

-- Access to CCLK pin
STARTUPE2_inst: STARTUPE2
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '1', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => flash_clk, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output
);

 

flash_clk is the clock generated by your logic.

 

Hope that helps 

 

regards

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10 Replies
Voyager
Voyager
1,708 Views
Registered: ‎08-16-2018

Re: Controlling SPI flash after configuration on Artix 7

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I thought the same, but I managed to do that. You don't need to specify or constraint the CCLK pin, it will come out there for you.

I used the quad SPI IP block on Artix-7, and enabled the STARTUP block inside it (not sure if a must). Then just constrained the 4 i/o and the CS pins. 

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Visitor element
Visitor
1,694 Views
Registered: ‎08-07-2017

Re: Controlling SPI flash after configuration on Artix 7

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That is great to hear that it is possible to access the configuration SPI flash from user logic.  From what I could find, the Quad SPI IP is AXI only?  I don't currently use any AXI based IP and haven't planned on it, due to the added complexity and lack of a CPU core, etc.

 

I have been using SPI master/slave modules from opencores.org with success.  Seeing as the CCLK_0 pin is special, the question remains if one of those open cores could be made to work with this.  Maybe the CCLK_0 line is always running and there is a way to access it for clocking a module?

 

Thanks for the confirmation that it works with the included Quad SPI AXI IP.

 

Best regards,

 

Element Green

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Voyager
Voyager
1,676 Views
Registered: ‎08-16-2018

Re: Controlling SPI flash after configuration on Artix 7

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@element,

It can be AXI-Lite. You could find a minimalist processor using less real estate than a microblaze (picoblaze?) for just communicating with your SPI. It's even possible to have your blocks talking to an AXI peripheral, but I think in that case you'd be better off implementing your SPI front end.

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Explorer
Explorer
1,647 Views
Registered: ‎06-13-2012

Re: Controlling SPI flash after configuration on Artix 7

Jump to solution

Hi @element,

 

if you've already a working front end and you just need to access the clk pin, instantiate the STARTUPE2

 

-- Access to CCLK pin
STARTUPE2_inst: STARTUPE2
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '1', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => flash_clk, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output
);

 

flash_clk is the clock generated by your logic.

 

Hope that helps 

 

regards

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Visitor element
Visitor
1,629 Views
Registered: ‎08-07-2017

Re: Controlling SPI flash after configuration on Artix 7

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Hello @auricm,

 

For some reason I didn't get an email notification for your reply.  I had just discovered the STARTUPE2 primitive and was coming back to the thread to post my findings, when I found your post.  Thank you, very helpful information.  It looks like I can just use the USRCCLKO input to directly drive the CCLK0 pin using the SPI master I am already using.

 

Best regards,

 

Element Green

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Explorer
Explorer
1,089 Views
Registered: ‎08-21-2013

Re: Controlling SPI flash after configuration on Artix 7

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@auricm, I have the exact same issue as @element and I think you pretty much cleared up my confusion. But just to double check, the SPI din, dout and CS configuration pins are multipurpose and can be used in user VHDL code after configuration. But the SPI config clock is not and we must use the STARTUPE2 to drive it from user logic. Is that correct?

One reason I'm confused is I have an Arty 7 board and their solution is to route the SCLK to both the configuration clock pin (E9) and a normal user IO (L16) as per D@n post here:

How to Program Arty FLASH

Is there any advantage to the way they did it on the Arty board?

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Explorer
Explorer
1,074 Views
Registered: ‎06-13-2012

Re: Controlling SPI flash after configuration on Artix 7

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Hi @corestar ,

you understood correctly, you must use the STARTUPE2 to drive CLK from user logic, I haven't found other ways.

If you don't want to use STARTUPE2 you can tie togheter two pins (with a resistor) as in Arty board but I don't see any advantage, you just lose one IO pin only to avoid the STARTUPE2 instance. I have projects where I don't have free pins to use so I must use STARTUPE2 and other projects where a lot o IO pins are unused... so this is up to you. I prefer to use STARTUPE2.

Regards

 

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Explorer
Explorer
1,058 Views
Registered: ‎08-21-2013

Re: Controlling SPI flash after configuration on Artix 7

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Thanks@auricm ,  I'll give it a try on the Arty board using STARTUPE2 instead of the way they recommend. I'm low on pins as well.

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Scholar dgisselq
Scholar
1,046 Views
Registered: ‎05-21-2015

Re: Controlling SPI flash after configuration on Artix 7

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@corestar,

Actually, there is a very big advantage to tying the flash SCK pin to two I/O's: CCK and a general purpose I/O.  The advantage?  You can run the flash twice as fast!  (Unless there's a way to use a DDR I/O with a STARTUPE2 that I'm not familiar with ...)

As an example, this design for the Arty runs the flash SCK pin at 82 MHz, rather than 50MHz or even 41MHz.  The result is that you can read data from the flash twice as fast.

Dan  (Yes, that D@n is me)

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Explorer
Explorer
1,039 Views
Registered: ‎08-21-2013

Re: Controlling SPI flash after configuration on Artix 7

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@dgisselq  (or do you prefer Dan :-),

Thanks, the Arty scheme makes sense now. In my case, the speed is not very important (I'm just reading some serial numbers etc at power up) and I'd rather save the pin. I'm assuming the STARTUPE2 does not use a large amount of resources. But I can see how in some applications the increased speed would be a great advantage.

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