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198 Views
Registered: ‎07-25-2019

Current scan chain do not match expected vc707 evaluation board

Flash programming issue in VC707  evaluation board.

While programming the bit file its programmed successfully but while programming the mcs to flash ic its showing  error. I am attaching error pics please help. as soon as possible.

i am using vivado 2017.2

 

Untitled.png
flash1.png
flash2.png
flash_bit_file_program_done.png
flash.png
log_file.png
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1 Reply
iguo
Xilinx Employee
Xilinx Employee
122 Views
Registered: ‎08-10-2008

There are several issues from the attachements.

1. Set the mode pins to jtag when programming.

2. Separate Erase, Program and Verify options. Each time only run one.

3. Let Vivado automatically detects the jtag chain, and keep the cable frequency low.

4. From the sceenshot you've got one programming working? But failed with no debug core? If this is the case, there maybe some SI issues as well. The debug core should be with a free running clock, try not to use MMCM/PLL locked signals for it.

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