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Observer
Observer
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Registered: ‎02-15-2016

Cypress S29GL01GS11FHIV20

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I have a Virtex 7 PCB design that used a Micron flash, P/N MT28GU01GAAA1EGC-0SIT. This part has gone obsolete, and I am in a position where this design has to be re-spun ASAP and I need to use a Cypress (formerly Spansion) flash, P/N S29GL01GS11FHIV20.

 

This part is listed Xilinx's documentation as being compatible and is also in the Vivado tool for programming configuration memory, so I am sure this part will work. However, the Cypress part is an asynchronous part whereas the previous Micron part was synchronous.

 

I am using the x16 BPI configuration mode. The pins on the new part are basically the same as the original except the new part does not have a clock pin. I am pretty sure the various enable pins (OE, WE, CE, Reset and WP, as well as the RY/BY) will handle the data transfer during configuration, but want to be absolutely sure there are no other ramifications or impacts to the configuration operation.

 

Has anyone done a design with the Cypress/Spansion flash that may have some insight and/or cautions?

 

 

 

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Moderator
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Registered: ‎01-15-2008

S29GL01GS flash is tested for asynchronous bpi flash configuration and as you are aware this is listed in ug908 which is supported.

So if you have followed the asynchronous bpi interface which we have provided in ug470, then you should not face issues in using vivado hardware manager for programming and this flash should be able to configure the fpga

 

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Moderator
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Registered: ‎01-15-2008

S29GL01GS flash is tested for asynchronous bpi flash configuration and as you are aware this is listed in ug908 which is supported.

So if you have followed the asynchronous bpi interface which we have provided in ug470, then you should not face issues in using vivado hardware manager for programming and this flash should be able to configure the fpga

 

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Observer
Observer
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Registered: ‎02-15-2016

Thanks for your answer. I am still not clear on setting this up in Vivado. In the "Edit Device Properties" dialog under "Configuration Modes" there is only a choice for Master BPI using a synchronous device (at least that is what the attached schematic in the Vivado dialog shows) . The Asynchronous device schematic shown in the "7 Series Configuration Guide" has the CCLK and ADV_B pins disconnected. I also don't see any other settings that seem to pertain to asynchronous operation, other than the Synchronous Mode Disable. Is this the only setting I need to worry about?

 

I am assuming selecting the Master BPI mode will work regardless of whether a synchronous or asynchronous part is in place, but want to make absolutely sure. A board re-spin depends on this, as well as a tight production schedule, so a mistake on this would be catastrophic.

 

Thanks for your help on this.

Master_BPI.PNG
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Registered: ‎01-15-2008

you need to follow the BPI asynchronous interface provided in UG470 which is attached to this post.

Vivado shows up the cclk connections, however for asynchronous you dont need.

You can refer to the following App note  for BPI interface which was for Virtex-5 but should be of help.

https://www.xilinx.com/support/documentation/application_notes/xapp973.pdf

 

bpi.JPG
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