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prasanthvthycaud
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Registered: ‎12-24-2013

Diiferent ways to program/load the bit files into the onboard flash

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Hi All,

 

I am developing an Ethernet System in which the device has a Kintex-7 FPGA  which has an on-board Flash to store/load the bit files into FPGA. Right now I am using Xilinx Programmer to load the bit files via JTAG. I would like to know, other than using Xilinx Programmer (JTAG) is the bit files can be loaded in to the on-board Flash? If yes, can you please guide me.

 

Regards,

Prasanth

 

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Registered: ‎01-22-2015

Hi prasanthvthycaud,


I suspect you are trying to remotely update the FPGA configuration stored in flash memory?


Comments from kkn are a start.  That is, after the FPGA is up and running, you can access all connections between the FPGA and the flash as ordinary I/O except the clock connection to flash, which you must access via the STARTUPE2 primitive (see ug953).


Now that you know the necessary hardware connections exist, you need to learn how to:
• Create a .bin version of the configuration file (not .bit nor .mcs)
• Decide how to transmit the .bin file into the FPGA
• Learn how to write the .bin file from the FPGA to the flash
• Think about using Multiboot techniques
 
Creating the .bin file with Vivado is easy. Go to “Tools > Settings > Bitstream” and check “-bin-file”.  Remotely sending the .bin file into the FPGA can be tricky.  We have a LAN-to-RS232 convertor (Lantronix XP1001000-05R) on our FPGA board.  So, we can send the .bin file over our local network to the board and the FPGA ends up getting the file via the RS232 connection with the Lantronix convertor.  The FPGA then sends the .bin file to the flash using HDL code similar to what you’ll find in XAPP1081.

 

Finally, you’ll want to consider Multiboot (see ug470, XAPP1246, XAPP1247).  In short, this is a technique where you partition the flash into two parts called the “golden” and “update” part.  Into the “golden” part you write a known-good configuration file using the Xilinx Programmer and JTAG interface.  After the FPGA is up and running with the golden configuration, you then use the remote update methods outlined above to write your .bin file into the “update” part of the flash.  When power is next cycled to your FPGA board, the FPGA will first try to configure itself from the file found in the “update” part of the flash.  If this fails, then the FPGA falls-back to configuring itself from the file found in the “golden” portion of the flash.


Mark

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kkn
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Registered: ‎01-15-2008

Hi Prasanth,

 

yes, you can use the onboard flash to store the bitstream if the flash is interfaced to dedicated IO pins for the spi/BPI flash interface.

Then you can use vivado programmer to convert bit file into mcs file and then program the flash with this mcs file.

refer to ug908 which helps in understanding the programming details 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug908-vivado-programming-debugging.pdf

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prasanthvthycaud
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Hi @kkn

 

Thank you for your reply.

 

I think I didn't mentioned the requirement clearly in my previous post. Right now I am following the same steps as u had mentioned, I convert the bit file into a mcs file and then I am programming the flash with the mcs file, for programming the flash I am using a Xilinx Platform Cable.

 

I wanted to know that is there any other option/way to program the flash by not using a Xilinx Platform Cable.

 

Regards,

Prasanth

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kkn
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Registered: ‎01-15-2008

Hi Prasanth,

 

is it SPI flash or BPI? which fpga device family are you using?

check the following links for ultrscale

spi => https://www.xilinx.com/support/documentation/application_notes/xapp1280-us-post-cnfg-flash-startupe3.pdf

 

BPI => https://www.xilinx.com/support/documentation/application_notes/xapp1282-us-post-cnfg-nor-axi-emp-ip.pdf

 

--Krishna

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prasanthvthycaud
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Hi Krishna,

 

It is SPI Flash (SPI PROM type N25Q128) and the FPGA used is a Kintex-7 (xc7k160tffg676-2).

 

Regards,

Prasanth

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kkn
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you can use startupe2 primitive instead of startupe3 primitive mentioned in xapp1280 for post  config access of spi flash for read and write.

 

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Registered: ‎01-22-2015

Hi prasanthvthycaud,


I suspect you are trying to remotely update the FPGA configuration stored in flash memory?


Comments from kkn are a start.  That is, after the FPGA is up and running, you can access all connections between the FPGA and the flash as ordinary I/O except the clock connection to flash, which you must access via the STARTUPE2 primitive (see ug953).


Now that you know the necessary hardware connections exist, you need to learn how to:
• Create a .bin version of the configuration file (not .bit nor .mcs)
• Decide how to transmit the .bin file into the FPGA
• Learn how to write the .bin file from the FPGA to the flash
• Think about using Multiboot techniques
 
Creating the .bin file with Vivado is easy. Go to “Tools > Settings > Bitstream” and check “-bin-file”.  Remotely sending the .bin file into the FPGA can be tricky.  We have a LAN-to-RS232 convertor (Lantronix XP1001000-05R) on our FPGA board.  So, we can send the .bin file over our local network to the board and the FPGA ends up getting the file via the RS232 connection with the Lantronix convertor.  The FPGA then sends the .bin file to the flash using HDL code similar to what you’ll find in XAPP1081.

 

Finally, you’ll want to consider Multiboot (see ug470, XAPP1246, XAPP1247).  In short, this is a technique where you partition the flash into two parts called the “golden” and “update” part.  Into the “golden” part you write a known-good configuration file using the Xilinx Programmer and JTAG interface.  After the FPGA is up and running with the golden configuration, you then use the remote update methods outlined above to write your .bin file into the “update” part of the flash.  When power is next cycled to your FPGA board, the FPGA will first try to configure itself from the file found in the “update” part of the flash.  If this fails, then the FPGA falls-back to configuring itself from the file found in the “golden” portion of the flash.


Mark

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prasanthvthycaud
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Registered: ‎12-24-2013

Hi markg@prosensing.com

 

Yes, I was trying to update the FPGA configuration stored in flash memory remotely. Thank you for providing the details.

 

Regards,

Prasanth

 

 

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@prasanthvthycaud

 

You're welcome!   Making all this work will take some time.  Feel free to send questions to me via this post - anytime.

 

Mark

 

 

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prasanthvthycaud
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Hi markg@prosensing.com

 

As suggested, I had looked into the different XAPP documents which u had provided for Multiboot techniques.

 

I have a doubt on "Learn how to write the .bin file from the FPGA to the flash", I think I didn't mentioned about the system, My system is a PC based solution for which the bit files are loaded into FPGA via USB 2.0 and FPGA is configured as "Slave SelectMAP Mode". If I want to configure the Flash is it require to change the FPGA Configuration Mode?

 

Regards,

Prasanth

 

 

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Registered: ‎01-22-2015

Hi Prasanth,

              

                FPGA is configured as "Slave SelectMAP Mode"

Do you mean that when FPGA is powered-up you will *always* configure the FPGA from your PC?

 

Please see Table 2-1 on page 21 of ug470. The logic levels that you apply to FPGA pins M[2:0] indicate how the FPGA will be configured at power-up.  

 

For Slave SelectMAP mode, you will use M[2:0]=110 and the physical connections shown on page 42 of ug470. Note that flash memory is not used.

 

However, if you want the FPGA to read a configuration file from flash memory at power-up then you need to select one of the flash modes. We use “Master SPI, M[2:0]=001”, with physical connections shown on page 52 of ug470.

 

Page 141 of ug470 says that “The MultiBoot and fallback feature can be used with all master configuration modes.”.   So, MultiBoot can be used with “Master SPI, M[2:0]=001” mode but cannot be used with “Slave SelectMAP, M[2:0]=110” mode.

 

Cheers,

Mark