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gdoraisa
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Registered: ‎06-23-2021

Direct bitstream loading from SPI flash to FPGA

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Can Xilinx FPGA load bitstream directly from connected serial flash. Is there serial flash loader IP for the FPGA? The device is Artix-7 and there is no Microblaze. So is there an IP or macro instantiate for FPGA to reload bitstream from external serial flash directly.

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barriet
Xilinx Employee
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Registered: ‎08-13-2007

A7 can load from SPI directly - this is called Master SPI... No user IP is needed - or even could be needed as the FPGA isn't configured yet... This is hardened/dedicated logic called the configuration engine.


Yes, dedicated pins are involved. The FPGA knows the configuration mode desired by the board-level mode (M[2:0]) pins.

See https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf as suggested - particularly pages 50+ for the details as suggested above.

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joancab
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Registered: ‎05-11-2015

"loading the bitstream" is called configuration. There is a number of options depending on the configuration bits. One of them is QSPI flash, that I think, can be a SPI flash.

Configuration happens automatically at power up or reset. 

When you say "is there an IP or macro instantiate for FPGA to reload bitstream" you may mean reconfiguration or even partial reconfiguration. Yes, a configured FPGA can do that.

It is also possible to access the configuration memory as such, for example to write a configuration upgrade so the next time it boots -tadah- new version.  

All the answers should be in the Artix 7 configuration user guide 

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gdoraisa
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Registered: ‎06-23-2021

My question is can the Artix-7 on power-up load bitstream from SPI flash directly  (no external CPU involved). Is IP needed or dedicated pins from FPGA connected to serial flash directly?

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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

A7 can load from SPI directly - this is called Master SPI... No user IP is needed - or even could be needed as the FPGA isn't configured yet... This is hardened/dedicated logic called the configuration engine.


Yes, dedicated pins are involved. The FPGA knows the configuration mode desired by the board-level mode (M[2:0]) pins.

See https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf as suggested - particularly pages 50+ for the details as suggested above.

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