10-21-2020 05:16 AM - edited 10-21-2020 05:28 AM
Dear experts and friends, we are trying to do some reconfigurable design on vu37p (SSI device). The development environment is VIVADO2019.1
With reference to the design of xapp1292, some reconfigurable bitstream files need to be converted to .bin files, and then parsed and transferred to the input of ICAP primitives after being transmitted through the TFTP network. The conversion method of xapp1292 is as follows:
We first downloaded some reconfigurable files directly through JTAG in the VIVADO environment, and verified that these partially reconfigurable files can be used normally. When converting a .bit file to a .bin file, VIVADO gave the following warning:
WARNING: [Writecfgmem 68-32] Bitfile /home/vu37p/tftp/20201013B/inst_count_RM_count_down_partial.bit is a partial reconfiguration bitfile. It is not possible to validate that this bitfile is compatible with the SMAPX32 interface.
At the same time, we tried to use different interface options such as SERIALx1, SPIx4, BPIx16, etc., and the same warning appeared.
Nevertheless, .bin files can be generated. But when we tried to burn this .bin file to vu37p, VIVADO gave this error:
ERROR: [Labtools 27-3157] File Error: Programming bin file not supported for SSIT devices
The design-related .bit and .bin files are attached. This problem has troubled us for a long time, and there is no similar error analysis on Google. Is there anything special about SSIT FPGAs like vu37p in their .bin files , when we doing partially reconfigurable designs?
We are grateful if you can provide some solutions