cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Visitor
Visitor
173 Views
Registered: ‎09-30-2020

ERROR while bitstream generation for VC707 MIG DDR3 project

I am following below pdf for generating  DDR3 test project using MIG for VC707.

https://www.xilinx.com/support/documentation/boards_and_kits/vc707/2014_3/xtp206-vc707-mig-c-2014-3.pdf

and I am getting below error while bitstream generation.

General Messages[IP_Flow 19-4299] Failed to copy 'c:/vc707_mig/vc707_mig.srcs/sources_1/ip/mig_7series_0/mig_7series_0.dcp' to 'c:/vc707_mig/mig_7series_0_ex/mig_7series_0_ex.srcs/sources_1/ip/mig_7series_0/mig_7series_0.dcp'
[Common 17-161] Invalid option value '' specified for 'objects'.
[Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ImplementationDesign Initialization[Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports clk200p]'. ["c:/vc707_mig/mig_7series_0_ex/imports/example_top.xdc":2]
[Common 17-55] 'set_property' expects at least one object. ["c:/vc707_mig/mig_7series_0_ex/imports/example_top.xdc":5]
Write BitstreamDRCPin Planning[DRC NSTD-1] Unspecified I/O Standard: 2 out of 119 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: init_calib_complete, and tg_compare_error.
[DRC UCIO-1] Unconstrained Logical Port: 2 out of 119 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: init_calib_complete, and tg_compare_error.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

Can you give some suggestion?

 

 

0 Kudos
Reply
0 Replies