I'm using the Xilinx zcu102 development board. My design is PL only and I'm programming the FPGA via JTAG.
Since I'm using JTAG, The ZYNQ IP is not included into my Block Design yet. When I try to programmed the FPGA Vivado 2018.2 returned this error:
ERROR: [Labtools 27-3176] hw_server failed during internal command. Resolution: Check that the hw_server is running and the hardware connectivity to the target
It take me 3 try before the FPGA can be programmed, otherwise I get the above error, also this is repeatable. Why is this occurring and how can I correct this?
Please go through debug checklist for zcu106 and follow the instructions on cable detection, jtag initialization and configuration.
Let us know if you still face issues.