UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor yubex
Visitor
2,187 Views
Registered: ‎04-10-2017

FUSE_DNA [6:0] ?

Hi Guys,

 

i am currently working on a kintex 7 design and i want to implement a register (which can be read by a link partner) which has an unique FPGA device ID in it...

Because the DNA_PORT value (57 Bit) is not unique, i plan to generate the FUSE_DNA value in my design.

We know from ug470 that the bits [63:7] of FUSE_DNA are defined as the value from DNA_PORT [0:56].

But how are the bits [6:0] of FUSE_DNA defined?

 

Thanks.

 

0 Kudos
3 Replies
Scholar austin
Scholar
2,162 Views
Registered: ‎02-27-2008

Re: FUSE_DNA [6:0] ?

y,

 

Those are for you to assign in your design.  It may be part of your configuration, or it may be a derived value you create.

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor yubex
Visitor
2,134 Views
Registered: ‎04-10-2017

Re: FUSE_DNA [6:0] ?

Hi austin,

thanks for your reply.

 

It would be ideal to have the same value in my register as FUSE_DNA would provide when somebody reads it per JTAG...

-> to be consistent.

So anybody knows how the Bits [6:0] are defined?

I will try to find it out by myself..

-> if i dont find it out i will define something by myself like austin recommended.

 

 

 

 

 

0 Kudos
Observer kwame.kyere
Observer
453 Views
Registered: ‎02-24-2016

Re: FUSE_DNA [6:0] ?

Hello,

 

please how did you go about it? Did you define something as recommended by Austin ?. I am currently having a similar challenge and i would like to know how you went about solving it.

Thank you.

 

 

Best regards,

 

Kwame

0 Kudos