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rizwantariq
Contributor
Contributor
304 Views
Registered: ‎06-21-2017

Fault Injection in HDL design

Hello,

I am working in the area of Fault-Tolerant AI processing for safety-critical applications. I would like to get your opinion on the topic of fault injection in FPGA design. Which method should i follow to do fault analysis of the FPGA design (in my case the design is a CNN)

Query:

I have CNN (convolutional neural network) implemented on ZCU102 FPGA. I would like to do a fault analysis of this CNN. And after fault analysis, I would like to work on different methods to make the CNN fault-tolerant. So there are these two methods which I am currently looking for fault injection

  • Cadence Xcelium Fault Injection tool
    • it supports RTL level fault injection. 
    • Vivado supports third party simulators. and in this case, Cadence Xcelium fault injection flow can come in handy.  
  • Fault Injection in FPGA bitstream.
    • in different research papers, i also came across this method, in which people are directly injecting fault in the configuration bitstream of the FPGA.

I would like to get some guidance on which one I should choose.

Please refer me any material/userguides/reference designs/links related to this ?

Are there any better suggestions/methods to do the fault analysis ?

  

some more info: 

Vivado Version: 2019.1

FPGA platform : ZCU102 and VCU118.

 

Thanks a lot

Best regards
Riz

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2 Replies
Ammar_k
Xilinx Employee
Xilinx Employee
188 Views
Registered: ‎03-29-2021

Hi Riz,

Hope you are safe and doing well.

For error injection in FPGA you can follow the below link once:-
https://www.xilinx.com/support/answers/61241.html.


Regards,
Ammar.

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rizwantariq
Contributor
Contributor
150 Views
Registered: ‎06-21-2017

Thanks Ammar. I Will go through the link you provided. 

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