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vovatkaswraith
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Registered: ‎07-07-2020

Flash-memory

The attached file contains schematic of the Master SPI Configuration Mode, which uses the same configuration in both flash-memory. Is it possible to use different configurations in different flash memory? And how do I manage the selection of flash memory used?

To work, I need to have two different configurations (on two different flash memory) that will then be switched by external influence

H0nPnZJtJoA.jpg
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hj
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Registered: ‎06-05-2013

No, you cannot use different configurations in a primary and secondary flash. Although you can use a multiboot feature. https://www.xilinx.com/support/answers/70170.html

Refer to UG570 page#52.

To generate a bitstream for x8 SPI mode, the bitstream should be generated with the property CONFIG_MODE to SPIx8. For x8 SPI configuration, the primary flash must contain the initial portion of a configuration bitstream that includes the x8 SPI configuration command. When the FPGA reads in this command, it will issue either Quad Output Fast Read (6Bh) or Quad Output Fast Read, 32-bit address (6Ch) simultaneously to both the primary and secondary flash memories. The secondary flash should contain dummy information that is equal in size to the initial portion of the bitstream in the primary flash. Beginning at the next address after the initial portion of the bitstream in the primary flash and after the dummy data in the secondary flash, the configuration bitstream is split evenly between the flash devices beginning with the first four bits in the primary flash and the next four bits in the secondary flash.

The entire configuration bitstream will then be split between the two flash devices with the least significant nibble of each byte in the primary flash and the most significant nibble at the same address in the secondary flash.

The x8 SPI master configuration mode requires that the flash devices be identical and identically configured. For example, some flash devices have programmable latency or dummy cycles via nonvolatile configuration bits that may need to be set to allow high clock rates for the read commands. The latency cycles must be the same between the primary and secondary flash devices in order to maintain bit alignment.

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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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