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nadaumtimuj
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Registered: ‎01-29-2021

For loop index resource utilization

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For loop indices are wasting large resource after synthesis and implementation. I have multiple loops in my design, and so multiple indices. A single index is creating 32 registers. Is there any way to avoid it?

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hpbhat
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Registered: ‎02-08-2021

Hi,

If you want to use FOR loop as in case of any other programming languages like C/python/C++, then it will not be synthesized as you want. The for loop will give the Simulation results but it is not synthesizable if it is written as in any other programming language. In HDL, for loop is used to duplicate the circuits.  That is the reason why you are seeing 32 registers instead of a single register. It is the expected synthesis behaviour of a for statement in HDL.

HDL(Verilog/VHDL) is not a programming language but Hardware Description Language. 

 

With Regards,

HPB

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hpbhat
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Registered: ‎02-08-2021

Hi,

If you want to use FOR loop as in case of any other programming languages like C/python/C++, then it will not be synthesized as you want. The for loop will give the Simulation results but it is not synthesizable if it is written as in any other programming language. In HDL, for loop is used to duplicate the circuits.  That is the reason why you are seeing 32 registers instead of a single register. It is the expected synthesis behaviour of a for statement in HDL.

HDL(Verilog/VHDL) is not a programming language but Hardware Description Language. 

 

With Regards,

HPB

View solution in original post