Forwarding clock to output with ODDR

[Zz13]

Hello,

I am trying to forward my system clock to an output pin of my arty s7 50 board. I followed the instantiation in the language template. Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ODDR_instiation is
Port ( InputClock : in STD_LOGIC;
OutputClock : out STD_LOGIC);
end ODDR_instiation;

architecture Behavioral of ODDR_instiation is

begin
DDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => OutputClock, -- 1-bit DDR output
C => InputClock, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
--StopSignal <

end Behavioral;

In the top level domain I directly assigned InputClock => systemclock and OutputClock => 100mhzoutputOI.

I am seeing a 100 MHz signal on that port but it is far away from a square wave, looks more like a sine or delta voltage. The output voltage has a offset of 1.7V and a peak to peak voltage of 100 mV, which is really weird. You can see a picture of my measuring. I am using a really short (1 cm) jumper wire to measure the port with my oscilloscope probes.

I was expecting a square wave with 3.3V of amplitude and no offset. I have a feeling that something in my constraints (xdc file) is off:

set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports { systemclock }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200] 100 mhz
create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000} [get_ports { systemclock }]; #100mhz

set_property -dict { LOC V16 IOSTANDARD LVCMOS33 } [get_ports { 100mhzoutputOI}]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40].

I tried with LOC and Package pin but no big difference. I also tried putting an OBUF between ODDR and Output pin but still same thing. 

How can I get the output pin to output a clean square wave with 3.3 V of amplitude? What am I doing wrong?

Thanks for your help

[drjohnsmith]

thats nothing to do with the fpga
its your scope.

i bet you have either no ground wire on the probe, or a long one .
the probes come with a short clip that connects direct into the probe, giving you an earth of 10mm or so,

try that,
if it does not work, send us a picture of your probe and its earth connection.

[Zz13]

Hallo, I Tried as you Mentioned with the spring.but its still not a square wave somehow 

[avrumw]

This is most probably caused by a combination of two things...

By default, an LVCMOS33 output has a DRIVE strength of 12ma (which is probably sufficient) and a SLEW of slow. With a slow SLEW, it isn't clear that the output signal can go rail to rail in 5ns.

On top of that you are using a 1GSa/S oscilloscope which may be too slow to sample a 100MHz clock accurately.

These two together will make a square wave look not square.

Rest assured - inside the FPGA the 100MHz clock is perfectly normal...

Avrum

[Zz13]

Hi, I tried with Slew fast and 16 ma drive and a 10 mhz clock. I am still not getting a good square wave. 

My goal is to clock an external adc with the 100 mhz clock. But the signals doesnt Look really good. With the 10 mhz clock i am getring at least the right 3.3v level but still looks like a sine.

[markg@prosensing.com · Accepted solution]

@Zz13 

Please check the schematic for your Arty board.  I think the trace from pin V16 of the FPGA goes through a 200-ohm resistor, R7, before reaching the connector, JC, that you have shown.  Replacing R7 with a small piece of wire should square-up your clock output.

Also, check that the scope channel for your probe is set to high-impedance (and not 50-ohm).

Cheers,
Mark

[Zz13]

Hallo Mark,

I tried to output the clock on the differential pairs with 0 ohm Resistance. I simply assigned the clock to Jb_p1, but still no square. Maybe I cant Route the clock to differential output?

[markg@prosensing.com]

@Zz13 

JB_p1 comes from FPGA bank 14 pin, P17, and through resistor, R17.  VCCO_14 = 3.3V.

So, if you specify IOSTANDARD=LVCMOS33 for pin P17 - and you verify that R17= 0 ohms - then you should see a good square wave on a correctly setup oscope.

The FPGA pins P17 and P18 are a differential pair.  However, it will be difficult to use them for differential output because the bank voltage is 3.3V (see pages 92-93 of UG471(v1.10)) -  see also AR#43989.

Cheers,
Mark

[Zz13]

Hey Mark,

thank you for your helpful insights. With 1 MHz I am still getting a prwtty bad square signal. I think the Problem is the impedance of the trace from outputpin to fpga.

I think with a matching termination the problem should be gone.

Thanks

[markg@prosensing.com]

@Zz13 

At 1MHz you should see a perfect square wave on your oscope.

I'm pretty sure something is wrong with your oscope or setup of your oscope.

Some thoughts:

1. ensure your oscope probe/channel is set for high impedance (and not 50 ohm)
2. ensure your oscope probe has a good ground connection
3. ensure your oscope is set for maximum bandwidth
4. some probes have x10 and x1 settings - try them both
5. try using another probe
6. try using another oscope

Cheers,
Mark

[Zz13]

Hey Mark,

thank you for your advice. I tried to probe with 1:10 and it looks much better! I dont really know why but it looks much better. 

[markg@prosensing.com]

Capacitance associated with the 1:1 setting for a oscope probe can often load the circuit-under-test too much.  The 10:1 setting for the probe usually has much less capacitance.  See the following link for more information.

https://gpslimited.com/choosing-the-correct-probe-for-your-oscilloscope/