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nadaumtimuj
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Registered: ‎01-29-2021

I/O resource utilization

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I am using axi master to read my data. But still in my block design, I have to create output ports using "make external" to find them in the modules. Is there any way to avoid the output ports to minimize i/o resource utilization? Can I have virtual ports that I really don't need to assign to any board pins?

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hpbhat
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Registered: ‎02-08-2021

Hi,

I hope the AXI read data logic is also part of the same vivado design. As I understand, your concern is without taking out the AXI port, you want to interface your existing block diagram with the custom read logic using AXI. 

In that case, you can create a custom IP & connect the ports in the same block diagram itself.

http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorialAddIP.pdf

Refer page-11 onwards from above link.

Also, as far as the exported ports are not part of top module, exporting many ports internally will not result in increased IO utilization. 

With Regards,

HPB

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hpbhat
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Observer
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Registered: ‎02-08-2021

Hi,

I hope the AXI read data logic is also part of the same vivado design. As I understand, your concern is without taking out the AXI port, you want to interface your existing block diagram with the custom read logic using AXI. 

In that case, you can create a custom IP & connect the ports in the same block diagram itself.

http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorialAddIP.pdf

Refer page-11 onwards from above link.

Also, as far as the exported ports are not part of top module, exporting many ports internally will not result in increased IO utilization. 

With Regards,

HPB

View solution in original post