cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
yhtomit
Visitor
Visitor
435 Views
Registered: ‎07-18-2020

I2C read problem

Jump to solution

Hi

We are working on a solution that involves i2C communication between the XC7A35T-1FTG256C and FX3 development kit and are experiencing problems reading data from the FPGA registers.

What we are trying to do is to read a single byte of data from a register (0x40) of the FPGA, using the FX3. The transaction should be as shown in the first image, where the FX3 does this steps:

1. Send start condition
2. Send the device address followed by a write bit
3. Receive an ACK from FPGA
4. Send register address (0x40)
5. Receive an ACK from FPGA
6. Send repeated start condition
7. Send device address followed by read bit
8. Receive ACK from FPGA
9. Receive byte from FPGA register
10. Send ACK to FPGA
11. Send stop condition to FPGA

The issue is that the FX3 does not release the Bus after sending the device address followed by read bit to the FPGA (step 7). This prevents the FPGA from sending the register data to the FX3 board. What could cause this problem?

I have attached a second image that shows the result we get on the signal analyzer

 

Thanks.

 
Screenshot from 2020-07-17 17-16-52.png
Annotation 2020-07-19 083101.png
0 Kudos
1 Solution

Accepted Solutions
hellgate202
Visitor
Visitor
332 Views
Registered: ‎02-25-2018

Thanks for the reply, the problem was solved.

The problem was in wire connection between FX3 development kit and FPGA board. Now when we get the PCB with FPGA and FX3 on one board - problem was solved.

View solution in original post

0 Kudos
3 Replies
hellgate202
Visitor
Visitor
388 Views
Registered: ‎02-25-2018

I would like to add some comments to this topic. I'm an FPGA developer in this project.

For SDA/SCL lines i'm using IOBUF primitive such way:

IOBUF sda_iobuf
(
  .I  ( sda_o   ),
  .O  ( sda_i   ),
  .T  ( !sda_oe ),
  .IO ( sda_io  )
);

On the provided image of ILA timing diagrams first signal is sda_i, second one is sda_oe, third one is scl_i from SCL IOBUF. So the main question what could cause the condition when sda_oe goes low, but sda_i doesn't go high (external pull-up is present)

Tags (1)
0 Kudos
359 Views
Registered: ‎01-22-2015

@hellgate202 

...the main question what could cause the condition when sda_oe goes low, but sda_i doesn't go high (external pull-up is present).

A probable cause, as @yhtomit says, is that "...the FX3 does not release the Bus after sending the device address followed by read bit...".  That is, the FX3 is holding sda low.

I suspect there is some misunderstanding of how the FX3 (I2C master) communicates with the FPGA (I2C slave).  

I assume you are talking about the Infineon/Cypress FX3?  If you provide a reference to the FX3 I2C communications document, then perhaps someone can help solve the problem.

Mark

 

0 Kudos
hellgate202
Visitor
Visitor
333 Views
Registered: ‎02-25-2018

Thanks for the reply, the problem was solved.

The problem was in wire connection between FX3 development kit and FPGA board. Now when we get the PCB with FPGA and FX3 on one board - problem was solved.

View solution in original post

0 Kudos