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alex2301
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Registered: ‎11-02-2018

IDELAYCTRL problem

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Good day. An error occurs during implementation. I use UG953 to add IDELAYCTRL but don't understand how to make the port map?

[DRC PLIDC-10] IDELAYCTRL missing for IODELAYs: There are 1 IDELAY/ODELAY/IODELAY cells in the design which requires IDelayCtrl, but there is no IDelayCtrl cell

Used xc7z020clg400-1.

 

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pthakare
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Registered: ‎08-08-2017

Hi @alex2301 

I dont see IDELAYCTRL instantiation in VHD file you shared.

You have instantiated IDELAY and ISERDES but IDELAYCTRL is missing . Refer UG471 for details around IDELAYCTRL 

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pthakare
Moderator
Moderator
234 Views
Registered: ‎08-08-2017

Hi @alex2301 

I dont see IDELAYCTRL instantiation in VHD file you shared.

You have instantiated IDELAY and ISERDES but IDELAYCTRL is missing . Refer UG471 for details around IDELAYCTRL 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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alex2301
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Registered: ‎11-02-2018

I added IDELAYCTRL

IDELAYCTRL_inst : IDELAYCTRL
port map (
--RDY => open, -- 1-bit output: Ready output
REFCLK => clockADC, -- 1-bit input: Reference clock input
RST => resetn -- 1-bit input: Active high reset input
);

and changed IDELAYE2

DELAY_src=> "IDATAIN" 
and this solved the problem.

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