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joelschad
Adventurer
Adventurer
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Registered: ‎05-18-2018

JTAG plugging in/unplugging causing reset on Zynq UltraScale+

I am developing a design that uses XAZU2EG-1SFVA625Q. The part is configured in Vivado 2019.1.

My PS JTAG signals come into the dedicated 1.8 V pins in Bank 503.

When JTAG is plugged in or unplugged, the system resets, and it's unclear why.

All the pins of this bank will use the supply voltage applied to VCCO_PSIO3_503, correct? And there is no way to configure these pins to use any voltage beside whta is applied to that bank, correct?

Per UG1085, I have a pull-up on PS_DONE, to 1.8 V.

 

 

Any ideas what would cause this kind of resetting?

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Registered: ‎01-22-2015

@joelschad 

At our workplace we try to always use the following procedure:

  1. Attach the JTAG connector of the UNPOWERED programmer (eg. Platform Cable USB) to the UNPOWERED FPGA board.
  2. Power up the FPGA board.
  3. Plug the USB cable from the programmer into the PC
  4. Use Vivado/iMPACT to send configuration file directly to FPGA or to flash memory
  5. Close Vivado/iMPACT
  6. Unplug USB cable from the PC
  7. Power down the FPGA board
  8. Remove JTAG connector from the FPGA board

That is, I don't think the JTAG connection is designed for hot-plug or hot-unplug.

There is danger!  That is, suppose your programmer module is attached to the PC and the PC is sitting on some elevated voltage.  If you start plugging the JTAG connector onto the FPGA board and the GND pin isn't the first to connect then you could damage the FPGA! 

Also, programmer modules (eg. Platform Cable USB) often get partially powered from the JTAG pin, VREF.  So, as you push on the JTAG connector, VREF and the JTAG digital lines will be making intermittent contact.  This intermittent contact of the connector pins could send a undesirable JTAG message to the powered-up FPGA - which may cause the system resets you are seeing.

So, don't hot-plug or hot-unplug the JTAG connection.

Finally, power-cycling the board when the JTAG cable is connected can cause the FPGA configuration from flash to fail.  See AR#66954 for details.

Cheers,
Mark

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