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Visitor helgelangen
Registered: ‎01-24-2018

[Labtools 27-3157] File Error: Unable to find encryption file

I'm getting the above error message when trying to program an mcs file to the configuration flash memory attached to a Kintex Ultrascale FPGA on a custom board. I did use bitstream encryption for this project at one point, but I have now turned this off, and the FPGA in question does not have encryption keys programmed into its bbram or efuse memory. Why is Vivado requiring an encryption file when bitstream encryption is not enabled?

For the record, programming the FPGA with the (unencrypted) bitstream over JTAG works flawlessly, it's just when attempting mcs configuration that Vivado gives this error.

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Xilinx Employee
Xilinx Employee
Registered: ‎08-10-2008

回复: [Labtools 27-3157] File Error: Unable to find encryption file

You mentioned you did use the encryption feature. What operations did you run? Did you use the efuse or bbram?

Try to read out the FUSE_CNTL register from JTAG if you can, see what it is.

Don't forget to reply, kudo, and accept as solution.
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Visitor helgelangen
Registered: ‎01-24-2018

回复: [Labtools 27-3157] File Error: Unable to find encryption file

I only used bbram, and I am also now using a new FPGA board that has not been configured with encrypted bitstreams at all. And, as I said, it's no problem downloading unencrypted bitstreams through JTAG, it's Vivado itself that is prohibiting me from even starting programming the configuration flash because it's unable to find an encryption file.

What I discovered today, though, is that this is most certainly a bug in Vivado, which I can circumvent, although the process to circumvent it is cumbersome and time-consuming:

  1. First, I generate the unencrypted bitstream and then generate mcs/prm files from it
  2. I then enable bitstream encryption, and re-run synthesis, implementation and generation of an encrypted bitstream file
  3. When I then open the Vivado Hardware Manager, with a valid encryption file living in the runs/impl_1 folder (I presume this is what makes the difference), there's no more complaining about missing an encryption file
  4. I can then program the configuration flash using the unencrypted mcs files generated in step 1. No encryption keys have been downloaded to the FPGA's bbram or efuse key memories.

This is a pretty annoying bug that should be relayed to the Vivado development team. They should be able to reproduce by using any kind of Vivado RTL project, and:

  1. Enable bitstream encryption in a .xdc constraints file, using bbram as key location
  2. Generate an encrypted bitstream (and encryption key)
  3. Download both encryption key and bitstream to an fpga
  4. Disable bitstream encryption and generate new, unencrypted bitstream as well as mcs file for the configuration flash memory (ensuring that no encryption key file from step 2 survives when the workspace is wiped. Delete it manually if required)
  5. Power-cycle the fpga to ensure that the encryption key and configuration is wiped from memory (or clear it manually if you prefer)
  6. Try programming the configuration flash using the unencrypted mcs file. It should fail stating that no encryption file was found.

Not sure if all steps are needed to reproduce, but this is how it happens for me. Using Vivado 2018.2 and a Kintex Ultrascale KU115 FPGA on a custom board. The FPGA has 2x512 Mbit serial NOR flash attached to it in SPI x8 mode. The JTAG adapter is a Digilent HS3 dongle.

  1. Try programming the configuration flash with the
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