03-26-2019 03:23 AM
I've got a problem with my Microblaze application. After power up the FPGA works like desired but the Microblaze application doesn't start automatically.
- When I program the FPGA via SDK -> Xilinx -> Program FPGA with the current *.bit- and *.elf-file the application doesnt start automatically but the FPGA itself works.
- When I use Run As -> Launch on hardware (GDB) after programming the FPGA both FPGA and Microblaze application work.
- When I use Xilinx -> Program Flash with the current download.bit-file and reconnect the power supply the FPGA only works. With Launch on hardware (GDB) the application starts.
I'd be greatful if you can help me with this problem. The project worked fine with software version 2016.4. After migration to 2018.3 the problems occured.
Searching for a solution I found this thread:
To me it seems like being a similar problem. But as I am new to FPGA programming I didn't understand where to set the startup clock. (If it is the reason for my problem.)
- Trenz TE0725-03 with Artix-7 XC7A35T (CSG324 package)
- Xilinx Platform Cable USB II
Software where the problem occured:
- Vivado (2018.3)
- Xilinx SDK (2018.3)
Software without problems:
- Vivado (2016.4)
- Xilinx SDK (2016.4)
Thanks for your support!
03-26-2019 11:20 AM
03-26-2019 11:20 AM
04-16-2019 10:18 AM
04-17-2019 01:41 AM
Understanding that this patch can't help with 2018.2.
Do we know if the problem occurs in 2018.2, also?..
What can I do, instead?
I have a similar problem. Kintex Ultrascale with Microblaze + BRAM in the design. Design works well on 2016.1. After the upgrading to 2018.2, and many steps to make it be ready to synthesis>>end of SDK ready, I still don't see the Microblaze gets to work after reset\power cycle. When I use "debug on hardware (GDB) I can verify that the code (same as the version used for 2016.1 project) runs well..
06-24-2019 07:53 AM
I have a 2018.2 application and am not seeing it run at power up. Here are some questions:
1) Does the above mentioned issue occur with 2018.2?
2) Is there anything I need to do to allow the application to run after the fpga is programmed. e.g., I load the design with a jtag cable, is there a parameter or jtag related setting that I must set to allow the uBlaze to run?
09-12-2019 10:57 AM
I have a MB project running Vivado 2018.3.1 (there's no release note available, so I'm not sure what the .1 did). Some simple programs/designs worked fine even before the patch. This one (using a VC707 board) uses the DDR3 memory, an Ethernet IP and other fun complications. Even after applying the patch (using the XILINX_PATH approach since I don't have permissions to change the installation directory), I still have the same problem. Using the SDK "Run..." I can launch the program. Building the bitstream in either Vivado or the SDK does not launch the main().
09-12-2019 12:33 PM
Thanks for the info. I was wondering if you added the .elf file to your vivado project and then created the bitstream. This should embed the elf file within the .bit file.
I had some success, but still seem to have issues on occasion and I'm not sure why. (One board seemed to work, the other did not). I've since moved on to other things.
09-12-2019 01:43 PM
Yes, I included it, and associated the ELF with the MB in the Tools. That is the recipe IIRC, and I've done it successfully with two other (smaller) MB projects already no trouble. This one has more stuff (DRAM, Enet, etc.) so I'm thinking that is what's causing the failure. They may have uncovered the .mmi error for one type of problem but not for others. Or I could be doing something wrong. In setting up the linker script I believe I had it place all the text and data segments (the instructions and static data) into the local BRAM, since clearly you can't initialize DRAM via a BIT file. My biggest buffer right now is only about 30 kB so I don't necessarily need to use the DRAM (that's for growth). The malloc() calls (standalone OS) come back fine so I assume the system is "doing the right thing" there.