cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
kg1
Participant
Participant
1,795 Views
Registered: ‎04-03-2016

Microblaze boot from SD card

Is it possible to boot a Microblaze application from an SD card via AXI Quad SPI? And how do I implement it?

I know that this can be done using SPI flash by creating an SREC bootloader application and burning the SREC file at a specific location in SPI Flash. But can this be done via an SD card? 

I wish to be able to store the microblaze application on the SD card and load it into DDR memory. I couldn't find any information about this feature apart from those for Zynq FPGAs which uses a different system.

To clarify I DO NOT wish to program the FPGA via an SD card. I only want to load a Microblaze application.

I would appreciate any feedback on the above.

0 Kudos
13 Replies
williamk
Xilinx Employee
Xilinx Employee
1,758 Views
Registered: ‎05-21-2013

Are you still looking for a solution? If so, I can write a much lengthier explanation of how this can might be done. Just to clarify, you are running on an FPGA device, and when the device boots, it configures itself from the QSPI. Included in the bitstream is the description of the MicroBlaze processor which then uses an image on the SD card to load an application (usually an FSBL) which would then copy the user application to DDR.
Is this what you are looking to do?
0 Kudos
kg1
Participant
Participant
1,746 Views
Registered: ‎04-03-2016

Hi @williamk,

Thanks for your reply. Yes I am still looking for a solution and the intended use is as you described.

0 Kudos
williamk
Xilinx Employee
Xilinx Employee
1,739 Views
Registered: ‎05-21-2013

I think the "magic" is going to happen with the FSBL. if you load the BRAMs for the MicroBlaze processor with an FSBL that is configured to load from the SD card, then, the boot sequence can look like this...

From the hardware side you will need to:

1) create your hardware design with peripherals, caches, and whatever else you want. Make sure there is a DDR controller (which is covered in the next item...)

2) customize the MicroBlaze to use DDR. This will usually instantiate a DDR controller or use the DDR controller in the PS if you are using a Zynq device.

3) generate your bitstream as usual

From the software side:

1) Using the Vitis IDE, modify the FSBL so that it is set to only boot from the SD Card. This would be done by modifying the code in the platform project. (There are certain compiler SYMBOLS that can be selected to do this as well as removing unnecessary parts of the FSBL such as QSPI drivers. We have an educational module on debugging the FSBL which goes through much of this process. It's not too difficult and running through the example lab shows you how it is done. There will be some differences as the lab is geared towards the MPSoC devices, but the concepts are the same for the MicroBlaze).

2) Create an application project that you want to run from the DDR. This is just whatever it is that you need to run. The fact that it's running from DDR isn't that important - although you may want to visit the linker script to make sure that everything that you want is being placed in DDR. Check out our LinkerScript lesson as it discusses how to create your own sections and put them into the type of memory that you want. (There is both a lecture and lab on this). Typically, low-latency items such as scratch-pad data, interrupt handlers, etc. are kept in BRAM as it is available within a dozen clock cycles or so as opposed to DDR which can take up to a few hundred clock cycles to access. Remember that DDR is great for moving large volumes of data quickly, but stinks for pulling individual datum out.

3) Build a bootable image for the SD Card.

4) You can either load the FSBL into the MicroBlaze's BRAMs so that it runs the FSBL (which copies from the SD Card to DDR) as soon as the MicroBlaze is released from reset OR (easier) just leave the default boot code in the MicroBlaze's BRAMs and that will go out to the SD Card and load the FSBL into the BRAM, and run it. With the FSBL running, the code will be copied from the SD Card into DDR, then control will be transferred to it and you will have (hopefully) an operational MicroBlaze system.

Let me know if you want more details on anything...

 

kg1
Participant
Participant
1,662 Views
Registered: ‎04-03-2016

@williamk,

Thanks for your reply.

Vitis IDE 2019.2 and Vivado SDK 2019.1 do not offer FSBL application projects for Microblaze base systems. Is there a particular version that support Microblaze FSBL or is there some way to get around this?

0 Kudos
williamk
Xilinx Employee
Xilinx Employee
1,612 Views
Registered: ‎05-21-2013

I'm building up an example design in 2020.1 to see if an FSBL is available for the uB. I'm targeting a "pure" FPGA device, that is, no PS. Hopefully, I'll have some kind of answer for you tomorrow.

0 Kudos
kg1
Participant
Participant
1,584 Views
Registered: ‎04-03-2016

I thank you for your time while I look forward to your reply.
0 Kudos
kg1
Participant
Participant
1,522 Views
Registered: ‎04-03-2016

Hi @williamk,

Did you have any progress regarding this issue?

0 Kudos
williamk
Xilinx Employee
Xilinx Employee
1,462 Views
Registered: ‎05-21-2013

I created a MicroBlaze only design (very simple as we are only looking to see what the Vitis IDE is providing as support).

So far, I've exported the design from Vivado and created a platform project in the Vitis IDE. Unlike the MPSoC platforms, it appears as though the FSBL is not automatically generated. This may be because the MicroBlaze's BRAMs can be pre-loaded with the FSBL or the application.

When I attempt to create a new application project, (as you pointed out previously), I am not seeing an FSBL application template.

There is, however, an mba_fs_boot template, as well as an SREC and SREC SPI Boot loader.

There is a (dated) tutorial on the Arty board for the SREC [SPI] Boot loader here: https://www.avnet.com/opasdata/d120001/medias/docus/178/UG-AES-A7MB-7A35T-G-Arty-SREC-Bootloader-VIV2015-2-V1.pdf

I'll reach out to the Xilinx internal team to see why the old FSBL template is missing.

Thanks for your patience!

 

0 Kudos
williamk
Xilinx Employee
Xilinx Employee
1,441 Views
Registered: ‎05-21-2013

OK, so here's what I learned...

MicroBlaze never supported the FSBL - the FSBL is a Zynq-7000/MPSoC/RFSoC/... kind of thing. That said, there is the FS-Boot which is a minimal bootloader that can be loaded into the BRAM and does enough to get an SSBL (like U-Boot) up and running. U-Boot can definitely load from the SD card.

I'm currently browsing for documentation, but the long and short of it is this: use FS-Boot to load U-Boot and set up U-boot to load from the SD card.

0 Kudos
williamk
Xilinx Employee
Xilinx Employee
1,433 Views
Registered: ‎05-21-2013

And the follow-up:

Usually, FS-Boot is used for booting Linux, but because it brings in the more capable U-Boot, you'll probably want to use it.

It's here on the public Xilinx GitHub:

https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/mba_fs_boot

It’s tiny - all it does is init the config interface & UART, init the DDR, load the U-Boot into DDR, then hands-off control to U-Boot.

I hope this gets it done for you!

0 Kudos
williamk
Xilinx Employee
Xilinx Employee
1,356 Views
Registered: ‎05-21-2013

Just following up - did this solution work for you? If so, could you mark this as a solution or a kudo? If it didn't let me know what I can do to help you with this...
0 Kudos
warning_cao
Observer
Observer
1,143 Views
Registered: ‎06-06-2018

Now I am doing the same scheme to realize spi startup with xcvu440(2017.4).Disable the STARTUP2E primitive. I did not create an application, but directly created the srec SPI boot loader application project. but now we report an error when writing QSPI:
ERROR: [Xicom 50-48] Start address (0x00000000) is outside of the device memory range.
Can you give me some advice?Snipaste_2020-09-18_15-51-22.pngSnipaste_2020-09-18_15-49-24.pngSnipaste_2020-09-18_15-46-19.png

0 Kudos
claudiug
Contributor
Contributor
1,060 Views
Registered: ‎05-07-2018

Hi William,

I'm trying to get this working, too. Would you have any hints on how to compile fs-boot.elf from the Github repo? I noticed that this binary gets output when one does a Petalinux build for microblaze, but the build happens under the hood. One has to disable "rm_work" in build/conf/local.conf to get to a bsp+Makefile for compiling this baremetal app. I wish there were a more direct way of doing this rather than having to run petalinux-build.

I'll need to add IP to access SD card in FPGA and create driver for it, then use xilff for the fat file system, and hopefully with that I can download u-boot.elf from sdcard to DRAM.

This will require updating the code in fs-boot.c, which may not stay small enough. Not sure if linker script needs to be updated in that case.

The board I'm using (Digilent's NexysVideo) is able to download the bitfile embedded with fs-boot.elf (via updatemem) from FAT partition on SDcard (via microcontroller) but once FPGA is configured control is given to FPGA to access the SDcard.

Thanks,
Claudiu
0 Kudos