06-08-2021 02:55 PM
I'm working with a 7series FPGA and Vivado 2019.2, and I would like to get multiboot setup. Using xapp1247 as a guide, I'm able to generate a golden bitfile and an update bitfile and things work normally. However for my use case, I don't want to generate a separate golden bitfile and update bitfile; I want these two bitfiles to be built from the same implementation run, but one should have the "BITSTREAM.CONFIG.NEXT_CONFIG_ADDR <address>" property set and the other should not.
Can this be accomplished within Vivado? If not, would a script to modify one bitfile work?
06-11-2021 02:09 AM
I'm a little confused about the usecase. Do you actually want identical designs for both the Update and Golden image?
You will need to have separate bitstreams. However, you will not have to run through the whole flow again. There is a way to just update the settings and regenerate the next bitfile with new settings, be sure to change the name though of the bitfile though.
To not have to go through the synthesis and implementation again, any changes to constraints would need to be done via the set_property commands in the TCL console or use the Bitstream Settings GUI, in order for them to take affect. Simply changing the XDC is not enough.
I hope this helps.
06-16-2021 03:21 PM
Thank you for the reply Wendy.
Yes, I actually want identical designs (with slight firmware/BRAM changes). I don't have access to the relevant Bitstream Settings GUI and I don't seem to be able to run `set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR <addr> [current_design]` unless I first open up the implemented design. When I do so, the changes won't take effect until I save the design changes, at which point my implementation becomes out of date.
I worked around this problem by writing a python script to find the relevant writes to WBSTAR and the IPROG command in a given bitfile and updating them appropriately. As a bonus, this approach is also much faster than re-generating a bitfile.