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Voyager
Voyager
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Registered: ‎05-11-2015

Pinout for DDR with Ultrascale

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With the good old MIG for 7-series, there was that interactive tool in the MIG GUI to choose the banks and byte groups.

Now with the memory interface for Ultrascale+ I'm lost. There is a reference to the I/O and clock planning but not much about DDR pinout, so how to proceed?

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Xilinx Employee
Xilinx Employee
467 Views
Registered: ‎08-13-2007

This is probably a better question for the Memory Interfaces and NOC board - rather than the Config board - maybe a mod can move it.


but, US/US+ MIG product guide (pg150) references the Vivado pin planning guide here:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug899-vivado-io-clock-planning.pdf

Chapter 4 addresses the new flow here for I/O planning for memory interfaces - have you seen this?


Cheers,

bt

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Xilinx Employee
Xilinx Employee
468 Views
Registered: ‎08-13-2007

This is probably a better question for the Memory Interfaces and NOC board - rather than the Config board - maybe a mod can move it.


but, US/US+ MIG product guide (pg150) references the Vivado pin planning guide here:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug899-vivado-io-clock-planning.pdf

Chapter 4 addresses the new flow here for I/O planning for memory interfaces - have you seen this?


Cheers,

bt

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Voyager
Voyager
442 Views
Registered: ‎05-11-2015
Gotcha, cracking on it now
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