06-08-2020 04:24 AM
i am seriously confused regarding AXI DMA write transfer, if some one could help me out i will greatly appreciate it
So i am programming DMA in vhdl through a custom IP with axi lite master .
using a state machine
First i start the s2mm channel by enabling a start/stop bit
then i give the destination address of Block ram
then i write the length register with total number of bytes needed to be transferred
In my case, the streaming data i receive is 131 beats (each beat is 4 bytes) total 524 bytes from my own developed streaming IP
The length registered is also written with 524 value which i think should be same as the data coming from streaming source
Now as soon as length register is written the DMA starts taking the data in by asserting tready high and then on AXI full memory map side the data starts coming out. When the whole transfer is complete i read the status register and it shows me halted bit is asserted and along with it also asserts the DMA internal error bit. The IOC_irq and Err_irq bits are also asserted in status register.
can some one tell me, is this normal? or what could be wrong here?
can some one please explain the timing behavior of DMA as what should happen when in which sequence, I will greatly appreciate the help
06-08-2020 06:31 AM
Are you using an AXI4-Stream interface between your IP and the DMA input? If yes, are you properly driving the Tlast signal from your IP? Tlast should be low for all transfers except for the last transfer where it should go high to specify the end of the transfer.
06-08-2020 09:47 AM
thanks alot for your reply, greatly appreciate it
i have posted the image of my block diagram
AXIstream_0 you see is the IP which i developed which generates data on M_AXIS. its just a counter, counts to a fixed number and starts from 0 again. Data width is 32 bits.
AXILITEMASTER_0 you see is the one i use to configure registers in DMA, I have developed a state machine in it and programming 30h,48h,58h registers and then i check until the DMA halts and then i restart the DMA, but it doesnt restart even when i reprogram the registers, if i reset the DMA and then reprogram them, then it works but the subsequent DMA transfers are not correct and i am pretty sure something is wrong here. Please help
06-09-2020 06:38 AM
It can be hard to properly implement the AXI4 protocol. I would recommend adding the "AXI Protocol Checker" to your BD to verify that your state machine is properly implementing the AXI4-Lite protocol.
Second, I would recommend adding a System ILA to your design and hooking up the S_AXI_LITE, S_AXIS_S2MM and M_AXI_S2MM port from the DMA to the ILA. That will allow you to better see what is happening.
06-09-2020 07:47 AM
There are also some "known issues" with the S2MM controller.
It seems most who work with this core just work around these issues.