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Visitor
Visitor
1,225 Views
Registered: ‎08-04-2014

Readback Verify and Capture on SSI devices

Hi,

I am interested in implementing readback verify and capture using SelectMAP on Virtex 7 series (7V2000T) and Ultrascale (VU440) FPGAs. The configuration users guide for both families (UG470 and UG570) only mention readback command sequence for monolithic FPGAs but have no information on how to do the same for SSI devices with multiple SLRs. Where can i find command sequence for multiple SLR devices?

I looked into the RBA file of a bitstream (ascii file that contains the readback commands) and I notice that the readback is being done 4 times i.e. the monolithic readback sequence described in UG470 is performed 4 times once for each SLR (Virtex-7 2000T FPGA). Each iteration of readback sequence only differs by the IDCODE. So i believe by setting IDCODE values to correct SLR we want to target, we can readback from that corresponding SLR.

My assumption is, in order to do readback verify or capture from different SLRs, we need to write the IDCODE for each individual SLR before performing readback verify or capture using the command sequence described for monolithic dies. Is this correct? Is there anything else to it? Am i missing something?

I have tried to change the IDCODE (which was extracted from the bitstream) for each SLR before performing the readback based on the assumption above but every time i receive the same data i.e.
1. I set Master SLR IDCODE, perform monolithic readback command sequence, store the readback data.
2. Change the IDCODE to one of the Slave SLRs and again perform monolithic readback command sequence and store the data.

Both the data stored in step 1 and 2 above are identical which means the readback is not happening on the slave SLRs. Can someone suggest what i might be missing.

Attached is the command sequence for readback for SSI devices based on my understanding so far. Please go through and suggest if i missed something important.

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9 Replies
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Xilinx Employee
Xilinx Employee
1,117 Views
Registered: ‎06-13-2018

Re: Readback Verify and Capture on SSI devices

Hi @rajavenk,

We are looking into this internally. We will get back to you.

 

Regards,

Priyanka Patil

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Xilinx Employee
Xilinx Employee
1,033 Views
Registered: ‎01-21-2013

Re: Readback Verify and Capture on SSI devices

Hi @rajavenk, @panantra,

Some good references for Readback for monolithic devices which you are probably already aware of include the below.

UltraScale

7-series

 

We don’t have anything fully documented yet for SSI devices.

However, to address your queries directly.

 

“My assumption is, in order to do readback verify or capture from different SLRs, we need to write the IDCODE for each individual SLR before performing readback verify or capture using the command sequence described for monolithic dies. Is this correct? Is there anything else to it? Am i missing something?”

          There is one IDCODE per device, not per SLR.

          There is not an IDCODE read needed to do any readback even on the master. I’m not sure whether you read some documentation that led you to believe so?

 

“I have tried to change the IDCODE (which was extracted from the bitstream) for each SLR before performing the readback based on the assumption above but every time i receive the same data i.e.
1. I set Master SLR IDCODE, perform monolithic readback command sequence, store the readback data.
2. Change the IDCODE to one of the Slave SLRs and again perform monolithic readback command sequence and store the data.”

          These steps would be incorrect.

          For SSI devices, I would follow the sequence set out in XAPP1230, Table 5, Page 14, for the Master SLR.  

          Then you need to insert a Type2 write 134217727 words to Slave SLR. This command is needed to read the Slave SLR. We will be documenting this in the future.

                    So after the Sync word of the slave SLR sequence, you’d need 0x3003C000 and 0x57FFFFFF.

          I believe a colleague is assisting you with this sequence. Once we have that ironed out, we can post the update on this thread.

Thanks,
Wendy
Xilinx Technical Support
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Contributor
Contributor
479 Views
Registered: ‎11-06-2018

Re: Readback Verify and Capture on SSI devices

Hi @wduffy,

Have you guys documented this yet? If so, could you point me to it? Thank you.


I think the original author is not trying to read the IDCODE before performing the readback, instead, he is saying we need to write the IDCODE register. And each SLR has different IDCODE.


For example, I have a VCU118 board, it has a Ultrascale+ chip which has 3 SLRs. Here is what I found from the .rbt and .rba file.

  1. For the .rbt file, which is the bitstream in ASCII format. There are 3 different parts targeting 3 SLRs. Let's call them RBT_SLR_0, RBT_SLR_1, and RBT_SLR_2.
    1. RBT_SLR_0 looks normal.
      1. It writes to IDCODE with 0x4b31093.
      2. It writes to FAR with 0
      3. It writes to FDRI with an additional Type 2, which is 0x5065eadc.
    2. RBT_SLR_1 is slightly different.
      1. It writes 0x3003c000 with 0x50cbd9dc
      2. It writes to IDCODE with 0x4b22093.
      3. It writes to FAR with 0
      4. It writes to FDRI with an additional Type 2, which is 0x5065eadc
    3. RBT_SLR_2 is slightly different.
      1. It writes 0x3003c000 with 0x5065ece3
      2. It writes to IDCODE with 0x4b22093.
      3. It writes to FAR with 0
      4. It writes to FDRI with an additional Type 2, which is 0x5065eadc
  2.  For .rbd file which is the ASCII readback version. It also has 3 parts. Let's call them RBD_SLR_0, RBD_SLR_1, and RBD_SLR_2.
    1.  RBD_SLR_0
      1. It writes to IDCODE with 0x4b31093.
      2. It writes to FAR with 0
      3. It writes to FDRO with an additional Type 2, which is 0x4865eadc.
    2. RBD_SLR_1
      1. It writes 0x3003c000 with 0x50cbd9b2
      2. It writes to IDCODE with 0x4b22093.
      3. It writes to FAR with 0
      4. It writes to FDRI with an additional Type 2, which is 0x4865eadc
    3. RBD_SLR_2
      1. It writes 0x3003c000 with 0x5065ecce
      2. It writes to IDCODE with 0x4b22093.
      3. It writes to FAR with 0
      4. It writes to FDRI with an additional Type 2, which is 0x4865eadc

It looks like (correct me if I'm wrong):

  1. Each SLR's frame address start from 0?
    1. The bit offset in the generated .ll file is also just within an SLR?
  2. All SLR has the same number of frames?
  3. Each SLR has different IDs. Before Writing or reading upon a specific SLR, we must write the right IDCODE value into the registers


To this specific issue,

  1. what's 0x3003c000 mean? And what's the value associated with it means?
  2. Can we just readback a certain SLR's stuff with the commands presented in the .rba file?
  3. .. also a bonus one, I assume all the bits in the .msk, .msd, .rbd are affected?
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Contributor
Contributor
466 Views
Registered: ‎11-06-2018

Re: Readback Verify and Capture on SSI devices

I somehow managed to crack the layout of .msk and .rbd files for SSI devices. With my VCU118.

Assume each SLR region has N words

  • 93+25 words of padding
  • N words for SLR0
  • 4 words of crap
  • 93+25 words of padding
  • N words for SLR1
  • 4 words of crap
  • 93+25 words of padding
  • N words for SLR2

Is this correct? Or the SLRx order might be different?

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Xilinx Employee
Xilinx Employee
413 Views
Registered: ‎01-21-2013

Re: Readback Verify and Capture on SSI devices

Hi @lastweek918

 

I would always recommend starting a new post for your question.

 

For UltraScale+ FPGAs:

Overhead words information:

     UltraScale+ FPGAs: (1Frame +  overhead words) = (93 + 25) = 118 words

Words per frame size information:

     UltraScale+ FPGAs: 93

 

When reading back between SLRs you must use the Slave SLR command followed by the max word count for UltraScale+

This differs depending on whether you’re using ICAP or SelectMAP. Which are you using?

 

Master SLR can differ per device. You’d need to check Table 1-3 of UG570 v1.11 for your specific device.

 

Thanks,
Wendy
Xilinx Technical Support
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Highlighted
Visitor
Visitor
371 Views
Registered: ‎08-04-2014

Re: Readback Verify and Capture on SSI devices

I was able to get the readback working on SSI devices and found some issues with the document. Some things were missing and others a bit misleading; Either they likely don't apply for my device (Virtex 7 2000T) or no longer apply for any of the devices and it hasn't been removed from user guide yet.

1. In UG470, under Configuration Memory Read Procedure (SelectMAP), it details the a shutdown command, if i use this command, i can't readback correct values. I had to not send the shutdown (0x0000000B) command. 

2. In order to switch to SLR number x, you have follow essentially (This is not documented anywhere for some reason):

for (int i = 0; i < x; i++) {
    send 0x3003c000;
    send 0x57ffffff;
    send 0xFFFFFFFF;
    send 0x000000BB;
    send 0x11220044;
    send 0xFFFFFFFF;
    send 0xAA995566;
    send 0x02000000;
}
//and then follow the Configuration Memory Read Procedure given in SelectMAP

 

3. IDCODE has nothing to do with the readback as i originally thought :).

Hope this helps :)

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Contributor
Contributor
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Registered: ‎11-06-2018

Re: Readback Verify and Capture on SSI devices

Hi @rajavenk,

Thank you for the follow-up. I also managed to make the readback capture work on my VCU118 board. I used a MicroBlaze-based solution.

Quick question: have you looked into the generated MASK file? More specific, can you find your expected value in the MASK file when you apply the bit offset from .ll file?

And happy thanksgiving to you.
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Visitor
Visitor
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Registered: ‎08-04-2014

Re: Readback Verify and Capture on SSI devices

I am not too sure what you mean by "expected value in the MASK file when you apply the bit offset from .ll file". I only use mask for verify portion of the configuration and not for capture for which you would need the .ll file. I was able to read the logic state directly from the FPGA without applying any mask. 

 

I did notice that for verify portion, the documentation is again misleading or no longer accurate. In Verifying Readback Data section of UG470, it says the mask has to be applied to the readback data only, but i found that it was not enough. I had to apply the mask to both the golden reference bitfile and the readback data to get data to match.

 

Hope this helps :)

 

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Contributor
Contributor
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Registered: ‎11-06-2018

Re: Readback Verify and Capture on SSI devices

Hi @rajavenk,

Overall, I was trying to extrat states from the readback captured bitstream. Say I have a counter register that I want to readback.

The approach I took is as follows: 1) I first look at the .ll file, find bit offset of my counter register. 2) then I use this bit offset to find the specific bit in the MASK file. 3) Since this is a dynamic state, I expect this bit to be 1 in the MASK file. However, in my VCU118 mask file, it is 0. When I applied the same approach to other non-SSI devices, the MASK value is correct. (I have more details on another post that no one has answered yet, in case you are interested: https://forums.xilinx.com/t5/FPGA-Configuration/Issues-with-ll-and-msk-file-with-an-SSI-Ultrascale-chip-VCU118/m-p/1047253)

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