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Newbie
Newbie
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Registered: ‎07-02-2020

Reflow cooldown rate for Kintex Ultrascale KU040 - FVA1156 package

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Application notes indicate a cool down rate of 2 deg C/sec max.  To maintain fine grain structure in the solder joint, our cool down rate is typically 4.0-4.5 degrees C/sec.

Thwo questions;

1.  Is the 4.0 - 4.5 degree C/sec cool down acceptable?

2.  What is/are the potential problems with a cool down rate in excess of 2 degrees C/sec?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @charlee 

I will recommend you to re-read following statement from XAPP427:

"The key is to optimize cooling with minimal temperature differential between the top surface of the package and the solder joint area. The temperature differential between the top surface of the component and the solder balls should be maintained at less than 7°C during the critical region of the cooling phase of the reflow process. This critical region is the phase in which the balls are not completely solidified to the board yet, usually between the 200°C–217°C range. The best solution might be to divide the cooling section into multiple zones, with each zone operating at different temperatures to efficiently cool the parts."

So, if you optimize your cooling as specified  in above statement , you can cool down FPGA at 4.0 - 4.5 degree C/sec with out affecting FPGA device. 

Regards,
Bhushan

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hello @charlee 

I believe your inputs provide in your initial notes are based on "Table 7-1: Pb-Free Reflow Soldering Guidelines for Package Sizes Up to 45 mm x 45 mm : Ramp-down rate" provided in https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf  OR Table 1: Pb-Free Reflow Soldering Guidelines : Ramp Down rates provided in https://www.xilinx.com/support/documentation/application_notes/xapp427.pdf

As mentioned in XAPP427: "The key is to optimize cooling with minimal temperature differential between the top surface of the package and the solder joint area. The temperature differential between the top surface of the component and the solder balls should be maintained at less than 7°C during the critical region of the cooling phase of the reflow process. This critical region is the phase in which the balls are not completely solidified to the board yet, usually between the 200°C–217°C range. The best solution might be to divide the cooling section into multiple zones, with each zone
operating at different temperatures to efficiently cool the parts."

Regards,
Bhushan

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Newbie
Newbie
88 Views
Registered: ‎07-02-2020
The response does not answer the original two questions.
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Highlighted
Xilinx Employee
Xilinx Employee
61 Views
Registered: ‎03-07-2018

Hi @charlee 

I will recommend you to re-read following statement from XAPP427:

"The key is to optimize cooling with minimal temperature differential between the top surface of the package and the solder joint area. The temperature differential between the top surface of the component and the solder balls should be maintained at less than 7°C during the critical region of the cooling phase of the reflow process. This critical region is the phase in which the balls are not completely solidified to the board yet, usually between the 200°C–217°C range. The best solution might be to divide the cooling section into multiple zones, with each zone operating at different temperatures to efficiently cool the parts."

So, if you optimize your cooling as specified  in above statement , you can cool down FPGA at 4.0 - 4.5 degree C/sec with out affecting FPGA device. 

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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