09-16-2019 04:59 AM
I am using artix 7 FPGA I am using BSP in SDK for Spi data transfer it is taking 2us for CS to go high after data trasmission can i reduce the the delay i have also attached the image and have shown delay b/n them it is around 1.6us can i reduce the delay
09-17-2019 01:57 AM
Typically, when Chip Select (CS) pin is asserted for particular SPI flash, that SPI flash is available for use with FPGA / uC.
Flash vendor provides Setup, Hold and deselect time details of CS. For example: please check Micron M25P16 datasheet : Table 21: AC Specifications and Figure 25: Serial Input Timing.
I will recommend you to go through datasheet of your flash and accordingly change CS timings accordingly.
I hope this information helps.
09-19-2019 06:07 AM
09-19-2019 06:11 AM
what chip are you driving ?
do a quick check that you are also driving the cs pin 1 to 0, not Z to 0.