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Contributor
Contributor
193 Views
Registered: ‎06-18-2019

Regarding delay of cs after SPI transfer

I am using artix 7 FPGA I am using  BSP in SDK for Spi data transfer it is taking 2us for CS to go high after data trasmission can i reduce the the delay i have also attached the image and have shown delay b/n them it is around 1.6us can i reduce the delay 

Screenshot (5).png
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Xilinx Employee
Xilinx Employee
189 Views
Registered: ‎03-07-2018

Re: Regarding delay of cs after SPI transfer

Hello @prashanth_makam 

Typically, when Chip Select (CS) pin is asserted for particular SPI flash, that SPI flash is available for use with FPGA / uC.

Flash vendor provides Setup, Hold and deselect time details of CS. For example: please check Micron M25P16 datasheet : Table 21: AC Specifications and Figure 25: Serial Input Timing.

I will recommend you to go through datasheet of your flash and accordingly change CS timings accordingly.

I hope this information helps.

Regards,
Bhushan

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Contributor
Contributor
173 Views
Registered: ‎06-18-2019

Re: Regarding delay of cs after SPI transfer

Actually I am asking for the SPI transfer and not regarding flash iam using manual chip select in the SPI
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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Regarding delay of cs after SPI transfer

what chip are you driving ?

   do a quick check that you are also driving the cs pin 1 to 0, not Z to 0.

 

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Contributor
Contributor
164 Views
Registered: ‎06-18-2019

Re: Regarding delay of cs after SPI transfer

Iam doing from 1 to 0
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