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kieling
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Registered: ‎06-07-2018

Request: Spartan 6 Pull ups during SPI indirect programming using xc6slx45_spi.cor

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Hello, 

I am trying to use Indirect programming on my design and have the same problem as on the topic: 

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-pull-ups-during-SPI-indirect-programming-using/td-p/201743

 

I tried using the core posted from user j1s1e1 there, but it crashes at the end of the flash programming (Done pin still low?). With the original file I am able to flash succesfuly, but it crashes other components of my design due to the pull-ups. Maybe the file uploaded there has a slightly different configuration? 

 

Could anyone from Xilinx send me a xc6slx45_spi.cor core without pull-ups? 

 

Best regards,

Vitor

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kieling
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Registered: ‎06-07-2018

In case it might help someone in the future:

 

Through internal contact with Xilinx they sent me the attached bitfile which solved my problem. 

 

As a reminder, rename the .bit to xc6slx45_spi.cor and place it on the "data/spartan6/" to use it with Impact.

 

Best Regards, 

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iguo
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008
Hi k,

These files are really old even Xilinx people may not save them any longer.
Do you have SR access? It's better to file a SR to request for these files.

Thanks,
Ivy
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kieling
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Registered: ‎06-07-2018

I tried but I do not see the request on "My Service Requests" so I do not know if it worked.

 

Could you ask internally for the file for me?

 

 

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iguo
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

Hi k,

 

Test the attached file. This should be the pullnone version. If it cannot work, try to contact a local support people.

 

Thanks,

Ivy

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kieling
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Registered: ‎06-07-2018

Hi Iguo,

 

Thanks for the file. Unfortunately it behaves the same as the file I already had.

 

It definately does not have the pull-ups, but after the flashing process I get a  "done pin didnt go high". I suppose the flashing did not worked correctly and when trying to read from the Flash the bitfile is buggy. 

 

My guess is that this bitfile is still somewhat different from the most recent ISE 14.7 bitfile. (pull-ups / float is not the only difference).

 

I suppose the RTL for this module is not open sourced right?  Is it possible to ask someone to generate a new one with the most recent version of the ISE software? 

 

From the support I got a message that I need to ask my distributor to open such a SR about this. I really want to avoid it because I can bet it'll take ages.

 

Best regards

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kieling
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Registered: ‎06-07-2018

Bumping this to see if I can get further help

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kieling
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Registered: ‎06-07-2018

In case it might help someone in the future:

 

Through internal contact with Xilinx they sent me the attached bitfile which solved my problem. 

 

As a reminder, rename the .bit to xc6slx45_spi.cor and place it on the "data/spartan6/" to use it with Impact.

 

Best Regards, 

View solution in original post