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Observer
Observer
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Registered: ‎08-03-2017

SPI_BUSWIDTH

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Using Vivado 2018.3 on an Artix xc7a35tcsg325-1

I keep running "set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]",

which is accepted w/o errors.

Then when I attempt to run "Generate Bitstream" from the GUI, I get the following error:

  • [Writecfgmem 68-20] SPI_BUSWIDTH property is set to "1" on bitfile F:/XilinxProj/cdp_proto_x1a/cdp_proto_x1a.runs/impl_1/top.bit. This property has to be set to "4" to generate a configuration memory file for the SPIX4 interface. Please ensure that a valid value has been set for the property BITSTREAM.Config.SPI_buswidth and rerun this command.

1 - why does the bitstream generation need to know the spi width.  Isn't it only used with JTAG?

2- when I run the "get_property BITSTREAM.Config.SPI_BUSWIDTH [current_design]",

the system returns "4".

How can I fix this?

Thanks,

>>Eric

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Hi @eholtzclaw ,

I tried at my end, using Vivado 2018.3 and targetting xc7a35tcsg325-1. I delcared SPIx4 in XDC File and created BIT File succesfully and targetted MT25Q128 Flash (one of supported Flash for Artix7 device, given in UG908(v 2018.3)) to generate MCS File and succesfull in generating MCS File.

 

Then when I attempt to run "Generate Bitstream" from the GUI, I get the following error:

  • [Writecfgmem 68-20] SPI_BUSWIDTH property is set to "1" on bitfile F:/XilinxProj/cdp_proto_x1a/cdp_proto_x1a.runs/impl_1/top.bit. This property has to be set to "4" to generate a configuration memory file for the SPIX4 interface. Please ensure that a valid value has been set for the property BITSTREAM.Config.SPI_buswidth and rerun this command.

>>>> From the above error message, it indicates that, you are generating MCS File and not BIT File.

Error says, you have set Bus width as 1 in your BIT File and while creating MCS File you are chossing Bus width as SPIx4, which is not matching.

   >> Please share the SPI Flash part number you are targetting?

   >>Please share your Bitstream settings, after generating BIT File. For more information on Capturing BITSTREAM settings refer this AR#54073 . And also share me your XDC file.

1 - why does the bitstream generation need to know the spi width.  Isn't it only used with JTAG?

>>> For JTAG Mode, SPI width is not neccessary. But when you want to generate MCS File for SPI Flash then, SPI Width should be declared in BIT File.

 

 

 

Regards,
Deepak D N
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Hi @eholtzclaw ,

I tried at my end, using Vivado 2018.3 and targetting xc7a35tcsg325-1. I delcared SPIx4 in XDC File and created BIT File succesfully and targetted MT25Q128 Flash (one of supported Flash for Artix7 device, given in UG908(v 2018.3)) to generate MCS File and succesfull in generating MCS File.

 

Then when I attempt to run "Generate Bitstream" from the GUI, I get the following error:

  • [Writecfgmem 68-20] SPI_BUSWIDTH property is set to "1" on bitfile F:/XilinxProj/cdp_proto_x1a/cdp_proto_x1a.runs/impl_1/top.bit. This property has to be set to "4" to generate a configuration memory file for the SPIX4 interface. Please ensure that a valid value has been set for the property BITSTREAM.Config.SPI_buswidth and rerun this command.

>>>> From the above error message, it indicates that, you are generating MCS File and not BIT File.

Error says, you have set Bus width as 1 in your BIT File and while creating MCS File you are chossing Bus width as SPIx4, which is not matching.

   >> Please share the SPI Flash part number you are targetting?

   >>Please share your Bitstream settings, after generating BIT File. For more information on Capturing BITSTREAM settings refer this AR#54073 . And also share me your XDC file.

1 - why does the bitstream generation need to know the spi width.  Isn't it only used with JTAG?

>>> For JTAG Mode, SPI width is not neccessary. But when you want to generate MCS File for SPI Flash then, SPI Width should be declared in BIT File.

 

 

 

Regards,
Deepak D N
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Observer
Observer
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Registered: ‎08-03-2017

Hey Deepak -

Got it to work by closing and reopening the project.

I would still like to know the answers to my questions.  So, I am working on supplying your querries.

A little time, please.

 

Thanks,

>>Eric

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