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830 Views
Registered: ‎10-08-2014

SPI Flash vs FPGA power-up sequence

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Hello,

We have a question and I really appreciate if you can help us.

We are designing a pcb with an Artix-7. The configuration file will be saved to and uploaded to the FPGA from a Micron FLASH. However, we cannot be sure about the power up sequence of these two ICs.

As you know, Artix-7 has a specific power up sequence: VCCINT, VCCBRAM, VCCAUX and VCCO

We want to learn when should we apply the voltage to the FLASH for a neat configuration file upload from FLASH to FPGA?

  • Before all of the FPGA voltages (VCCINT)?
  • Before VCCBRAM?
  • Before VCCAUX?
  • Before VCCO?

We could not be able to find a specific explanation for this.

Thank you very much in advance.

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743 Views
Registered: ‎10-08-2014

Dear users,

Thank you for your help.

First, I checked flash datasheet. Then, ug470_7Series_Config document as you adviced. But, we need one more document to find Tpor (power-on reset time) which is ds181_Artix_7_Data_Sheet, page 58 for our case.

So, in short, we found our solution. Thank you.

View solution in original post

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simon
Xilinx Employee
Xilinx Employee
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Registered: ‎08-25-2010

Hi @isravisioncamera 

Need to check POR time for FPGA and SPI datasheet to ensure that the SPI flash is ready to receive commands before the FPGA starts its configuration procedure:

• Control the sequence of the power supplies such that the SPI flash is certain to be
powered and ready for asynchronous reads before the FPGA begins its configuration
procedure.
• Hold the FPGA INIT_B pin Low from power-up to delay the start of the FPGA
configuration procedure. Release the INIT_B pin to High after the SPI flash becomes
ready to receive commands.

Please see page 58, ug470:

https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

Thanks
Simon
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zhiq
Xilinx Employee
Xilinx Employee
800 Views
Registered: ‎06-02-2017

@isravisioncamera ,

In a word, you need to ensure the flash is ready when the FPGA start to read the configuration file after power on. If the power sequence on the board cannot guarantee this,you can hold on the init_b of our fpga to delay the reading process.

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744 Views
Registered: ‎10-08-2014

Dear users,

Thank you for your help.

First, I checked flash datasheet. Then, ug470_7Series_Config document as you adviced. But, we need one more document to find Tpor (power-on reset time) which is ds181_Artix_7_Data_Sheet, page 58 for our case.

So, in short, we found our solution. Thank you.

View solution in original post

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