I have done several of the Xilinx tutorials for black-box wrapping of HDL in Simulink but have not come across one yet where more than one HDL file is used. I have a fairly large HDL codebase with ~40 files.
My top file makes use of all the other files (which are contained within pre-defined libraries). I am doubtful as to whether wrapping my top file in a black-box (which I have done) in Simulink, will work.
I have a working Vivado project for this build but asides from that, I am unsure how I need to tell Simulink about the hierarchy/libraries/multiple files for correct synthesis and implementation. Do I need to supply accompanying tcl scripts? Is there a way to pass the Vivado project file to System Generator in Simulink?
I am happy to share my .slx, and Vivado project should you need it.
In looking to answer my own question, I have considered that perhaps I should look at including my HDL code-base in a Simulink Black Box by first making it into a custom IP. I'd hope that this would have the required detail for System Generator to synthesize a result (information about hierarchy, libraries etc).
I've found a solution to simulating and generating the custom IP package in Simulink but little information about how to start with just getting my IP into a Simulink build: