03-04-2019 01:38 PM
Hi Xilinx Community,
I'm currently developing a board that utilizes the LX45 version of the Spartan-6 FPGA (in the FG(G)484 package).
My design employs LVDS, with all the outputs in pairs on Bank 0 of the FPGA, and all the inputs on Bank 1.
One of the LVDS inputs goes to pins A3 and A4 (L1P_HSWAPEN_0 and L1N_VREF_0 respectively) however. I haven't observed any erroneous behavior, but I understand pin A3 is tied to the FPGA's HSWAP function. Nothing I could find in the Spartan-6 documentation suggested it wouldn't work, but can anyone tell me if this pin is indeed safe to use for LVDS at 3.3 V?
Thanks a lot,
03-04-2019 04:29 PM - edited 03-05-2019 03:04 AM
Welcome to the Xilinx Forum!
Pin B3 in the Spartan-6 (XC6SLX45-CSG484) is a special multifunction pin that perform the HSWAPEN function during power-up/configuration of the FPGA. When configuration is complete, this pin switches automatically to operate according to your constraints/settings (ie. as part of an LVDS input). For more information see “I/O Pins During Power-On and Configuration” on about page 45 of document, UG381.
On about page 28 of UG381, it says that LVDS_33 inputs can be placed in any I/O bank powered with VCCO=3.3V.
So, having pin, B3, function as both HSWAPEN and LVDS_33-input will work - and is safe. However, if you want the HSWAPEN function then you must drive your LVDS_33 input at B3 to the appropriate level before the start of FPGA configuration.
Finally, check that your LVDS_33 input at B3 does not exceed the Absolute Maximum Ratings for VIN shown in Table 1 of DS162.
03-05-2019 10:05 AM
I am reading page 45 of UG381:
"Therefore, to enable the internal pull-up resistors on the user I/O pins prior to completion of configuration, the HSWAPEN pin must be either connected directly to GND, or forced Low by another device on the board."
Firstly, it seems the pin "controls the internal pull-up resistors". I had read from a third party source that the pin affected RAM on the device... can you confirm this is *not* the case?
Secondly, since I have an LVDS MISO line going to HSWAPEN, I cannot simply ground the pin. Is there any way of programmatically ensuring (in Verilog for ex.) that this pin will be held low at power-up/configuration? Or do I need a physical device to drive it low?
Right now the device seems to be functioning, but I'm unsure if anything is guaranteeing that the HSWAPEN pin is low at start-up, since as I said it's just attached to a MISO line and defined as a LVDS 3.3V input in the firmware.
Thanks so much for the timely and informative reply,
03-05-2019 02:11 PM - edited 03-05-2019 02:13 PM
Firstly, it seems the pin "controls the internal pull-up resistors”.
Yes, as you have read, the logic level applied to the HSWAPEN pin affects some of the FPGA I/O pins during configuration of the FPGA. When HSWAPEN=0 then FPGA internal pull-up resistors are connected to some I/O pins. When HSWAPEN=1 then these I/O pins float.
I had read from a third party source that the pin affected RAM on the device... can you confirm this is *not* the case?
Document UG383 talks about Block RAM (BRAM) for the Spartan-6. I see nothing in this document about HSWAPEN. Typically, data is written-to and read-from BRAM after FPGA configuration. BRAM is not nonvolatile memory. What is your concern about BRAM?
I have an LVDS MISO line going to HSWAPEN… Is there any way of programmatically ensuring (in Verilog for ex.) that this pin will be held low at power-up/configuration?
There is nothing you can do in HDL (eg. Verilog) to control any FPGA pin during power-up/configuration of the FPGA. However, you can sometimes place an external pull-up (or pull-down) resistor on a line to help hold it in a certain state during power-up/configuration. Table 5-2 in UG380 shows that some Spartan-6 configuration pins have dedicated pull-up resistors (inside the FPGA) regardless of the state for HSWAPEN. These dedicated pull-ups may conflict with external pull-ups or pull-downs that you use. Table 5-2 shows that MISO does not have a dedicated pull-up resistor. So, you are free to place an external pull-down resistor on MISO to help hold it low (as you wanted) during configuration
03-06-2019 03:37 PM - edited 03-06-2019 03:37 PM
Thanks so much for the information. I think either the third-party misinformed me about the RAM, or I misunderstood their note.
It is my first time implementing LVDS so I appreciate the insight regarding pull-downs. I have to apologize for a clarification however- in the current verison of the board the HSWAPEN pin (A3) is being used for SCLK+, so the schematic would look something like (with R1 being the on-FPGA termination resistor):
Given the presence of the LVDS termination resistors, what is an appropriate value for the pull-down resistor R5?
Thanks again for your help!
03-07-2019 06:50 AM - edited 03-07-2019 06:52 AM
It is my first time implementing LVDS…
I understand you are trying to use LVDS_33 with pin (IO_L1P_HSWAPEN_0) of the FPGA. If so, then make sure VCCO=3.3V for bank-0 of the FPGA. See also Table 2 of DS162 for specs on VCCAUX when using LVDS_33. You are correctly using the 100-ohm termination recommended by Table 1-3 and Fig 1-18 in UG381. Make sure that the input/output voltage levels for your “Slave Device” are compatible with the LVDS_33 voltage levels for the FPGA shown in Table 10 of DS162.
...what is an appropriate value for the pull-down resistor R5?
I understand that the pin labeled SCLK+ is pin (IO_L1P_HSWAPEN_0) of the FPGA and that pulldown resistor, R5, in your schematic is how you plan to hold HSWAPEN low during FPGA configuration. First, holding HSWAPEN=0 during configuration is a good idea since it prevents many FPGA IO from floating. However, it would be wise for you to search through UG380 for references to HSWAPEN to see if/how HSWAPEN=1 can affect configuration of the FPGA (just in case we fail to achieve HSWAPEN=0). For example, Table 2-6 of UG380 says that if HSWAPEN=1 then you must connect CSO_B through an external pullup resistor to VCCO. Also, find the Figure (eg. Fig 2.2) in UG380 that corresponds to your flash-to-FPGA interface and make sure you are using all the external resistors recommended for the interface.
Now, about R5….
We need a value for R5 that is low enough to pull HSWAPEN low during FPGA configuration but not so low that it later causes LVDS_33 output from SCLK+/SCLK- to be out-of-spec.
Key to calculating the needed value for R5 is the specification of VIL(max) for HSWAPEN. Page-56 of UG380 says that “The Spartan-6 FPGA configuration I/Os use the LVCMOS slow slew rate 8 mA I/O standard”. So, I will assume that the HSWAPEN input uses LVCMOS33, which has VIL(max)=0.8V from Table 9 of DS162. Next, we need a value, RPU, for the internal pullup resistors of the FPGA, which AR#19024 says we can calculate as RPU=VCCO/IRPU. The value of IRPU is shown in Table 4 of DS162 to be 200-500uA for VCCO=3.3V – giving RPU values that range from 16.5K to 6.6K. Finally, I will assume that the Slave Device is a simple LVDS_33 receiver that supplies no current/voltage to the SCLK+/SCLK- lines.
So, during FPGA configuration, we have a circuit that looks something like the following.
Using VCCO=3.3V and RPU=6.6K, I calculate R5 needs to be smaller than 1064 ohms to make VH < VIL(max)=0.8V (ie. to hold HSWAPEN low during FPGA configuration).
Next, we need to calculate if R5=1064 causes LVDS_33 output on SCLK+/SCLK- to be out-of-spec. I’ll leave the exact calculation to you, but I suspect that all will be well. Finally, you may want to add a pulldown resister R6=R5 on the SCLK- line to achieve equal impedance for each line of the (SCLK+/SCLK-) LVDS pair.
03-07-2019 12:53 PM
" Also, find the Figure (eg. Fig 2.2) in UG380 that corresponds to your flash-to-FPGA interface and make sure you are using all the external resistors recommended for the interface."
I believe the flash interface is what I had read about the pin affecting the RAM (external and not internal to the chip). This is of significant interest in my case because this part of the design is not something I can modify.
"However, it would be wise for you to search through UG380 for references to HSWAPEN to see if/how HSWAPEN=1 can affect configuration of the FPGA (just in case we fail to achieve HSWAPEN=0"
Because of the aforementioned constraint on the design, the device will is known to fail if we fail to achieve HSWAPEN=0. I would be happy to proceed with the pull-down design as you very helpfully explained, but if it's not guaranteed to achieve HSWAPEN=0 at configuration then it seems the only way to achieve reliability is to just not use this pin. Can you confirm this?
Thanks again for your expertise, it has been very educational!
03-08-2019 05:22 AM
You are very welcome. It’s fun to think about these unusual designs.
…only way to achieve reliability is to just not use this pin. Can you confirm this?
In the analysis I’ve shown, there are uncertainties. If you have another LVDS pin-pair available, then best to use them for (SCLK+/SCLK-) -- and save yourself a lot of worry.
On your new circuit board, you might consider adding the zero-ohm resistors (R7, R8, R9, R10) shown in the sketch below. By installing only resistors (R7, R8), you can test the analysis that we’ve talked about. If things don’t work, then you can remove (R7, R8), install (R9, R10), and set R5=0 (a short) – to get things working. If you decide to do this kind of testing then I hope you’ll tell us about the results.
Thanks for the interesting problem!