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Visitor
Visitor
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Registered: ‎07-24-2013

Spartan 7 Fallback after CRC error does not work

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For a Spartan 7 I saved a Golden configuration to address 0 and an update configuration to address 400000 on the SPI flash. If I delete the start sequence (address 400000) the watchdog timer runs and the fallback configuration starts. If I delete a block between start and end sequence a CRC error occurs, but no fallback is executed.

What could be the cause?

ConfigStatus_GC.jpg

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Visitor
Visitor
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Registered: ‎07-24-2013

回复: Spartan 7 Fallback after CRC error does not work

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Yeah, that was the problem! So far I had

set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]

always combined with

set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x0000000 [current_design]

and that didn't work.

Many thanks for your help!

Best regards

Jens

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Spartan 7 Fallback after CRC error does not work

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You broke the command sequence in the config image. Fallback is not designed to delete a 'block of data'.

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Visitor
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Registered: ‎07-24-2013

回复: Spartan 7 Fallback after CRC error does not work

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If there is an error while writing the update configuration, the fallback configuration should run afterwards, what else do I need the fallback for?

Why does the watchdog timer not work in case of a missing data block?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Spartan 7 Fallback after CRC error does not work

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1. Lost of command sequence makes FPGA 'confused' at this situation.

2. Fallback can work in multiple erroneous conditions while missing a block of data is only one scenerio. In this situation, we suggest you program the Sync word at last or whole image from high address to low. If the upgrade is interrupted, as long as there is no Sync word read into FPGA, it never enters into this hang.

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Visitor
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Registered: ‎07-24-2013

回复: Spartan 7 Fallback after CRC error does not work

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I understand that if the command sequence is defect, the fallback cannot be triggered. However, the command sequence is complete in my case, there is only an error in the data area. Maybe the command sequence it self is not correct? I have set the following via xdc:

# for Golden Configuration

set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]

set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.TIMER_CFG 32'h00040000 [current_design]

set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]

set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x0400000 [current_design]

# for Update

set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]

set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.TIMER_CFG 32'h00040000 [current_design]

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Spartan 7 Fallback after CRC error does not work

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Show me a screen of exactly which data bytes you corrupt. 

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Visitor
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Registered: ‎07-24-2013

回复: Spartan 7 Fallback after CRC error does not work

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MCS-Data corrupt.jpg

 

An example looks like this:

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Spartan 7 Fallback after CRC error does not work

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These are pure data. FPGA should be able to handle this.

I just see you did not add this constraint to the update image:

set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]

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Visitor
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Registered: ‎07-24-2013

回复: Spartan 7 Fallback after CRC error does not work

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Yeah, that was the problem! So far I had

set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]

always combined with

set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x0000000 [current_design]

and that didn't work.

Many thanks for your help!

Best regards

Jens

View solution in original post

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