cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jhk
Visitor
Visitor
1,698 Views
Registered: ‎05-26-2015

Ultrascale Configuration Pins - not a valid pin name

Jump to solution

Hello,

 

I want to access an external spi-flash memory through a custom flash controller at a Kintex UltraScale XCKU115-FLVA1517.

The controller works fine with different FPGAs of the 7series. In the UltraScale Design I entcounter a problem when I try to add the configuration ports to the constraints file:

 

screenshot.png

 

Pin AB9, AE11, AD10, AC9, AD9 should be the dedicated configuration pins of the xcku115-flva1517. The relevant section of my constraints file is as follows:

 

set_property PACKAGE_PIN AB9 [get_ports qspi_config_spi_csn]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_config_spi_csn]
set_property PACKAGE_PIN AE11 [get_ports {qspi_config_spi_d[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {qspi_config_spi_d[0]}]
set_property PACKAGE_PIN AD10 [get_ports {qspi_config_spi_d[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {qspi_config_spi_d[1]}]
set_property PACKAGE_PIN AC9 [get_ports {qspi_config_spi_d[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {qspi_config_spi_d[2]}]
set_property PACKAGE_PIN AD9 [get_ports {qspi_config_spi_d[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {qspi_config_spi_d[3]}]

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

 

Do I miss something? Is there something different between UltraScale and 7series which might be relevant for my problem? Do I need some additional constraints to access the dedicated configuration pins with UltraScale?

 

 

Thanks in advance.

Jan

0 Kudos
1 Solution

Accepted Solutions
kkn
Moderator
Moderator
1,977 Views
Registered: ‎01-15-2008

in ultrascale the spi data pins d0 to d3 are in dedicated bank, so to use in your design you need to use startupe3 primitive

check the following 

https://www.xilinx.com/support/documentation/application_notes/xapp1280-us-post-cnfg-flash-startupe3.pdf

View solution in original post

4 Replies
gnarahar
Moderator
Moderator
1,677 Views
Registered: ‎07-23-2015

@jhk These are Dedicated Config Pins and cannot be user assigned. Check Page#27-28 of UG575. The pins you trying to lock are part of Bank 0. 

 

Are you sure you were doing it in 7-series? I believe you were locking them to Multi-function pins and not Dedicated pins in bank 0 of the 7-series device.  

 

 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

kkn
Moderator
Moderator
1,978 Views
Registered: ‎01-15-2008

in ultrascale the spi data pins d0 to d3 are in dedicated bank, so to use in your design you need to use startupe3 primitive

check the following 

https://www.xilinx.com/support/documentation/application_notes/xapp1280-us-post-cnfg-flash-startupe3.pdf

View solution in original post

jhk
Visitor
Visitor
1,662 Views
Registered: ‎05-26-2015

@gnaraharthanks for your reply.

 

You are right. UG575, p.28 says that the data pins and chip-select are dedicated for UltraScale whereas the corresponding pins in a 7series device are multi-function (UG475, p.27). I was able to access the configuration flash via my custom spi-controller with a XC7VX485T and some 7series Artix devices.

 

Best regards,

Jan

0 Kudos
jhk
Visitor
Visitor
1,660 Views
Registered: ‎05-26-2015

@kknthanks for your reply.

 

I will have a look at the XAPP1280 Application Note.

 

Best regards,

Jan

0 Kudos