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Adventurer
Adventurer
414 Views
Registered: ‎06-25-2012

Ultrascale+ Maximum Configuration Bank 0 input voltage

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I am working on an Ultrascale+ design which is implementing Slave SelectMap for configuration. The master operates at 3.3V. Obviously we need to do level translation for many of the I/O which are used in the configuration process.

My question is: Is it safe to pull INIT_B and DONE pins to 3.3V when VCCO_0 operates on 1.8V? I cannot find the relevant specification for this in DS922.

I did find there is an absolute maximum input voltage rating, Vin, but it is only specified for HD and HP I/O banks, but Bank 0 is neither of those.

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Xilinx Employee
Xilinx Employee
398 Views
Registered: ‎06-06-2018

Re: Ultrascale+ Maximum Configuration Bank 0 input voltage

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Hi @jsmithsrc,

INIT_B to a 4.7 kΩ pull-up resistor to VCCO_0 to ensure clean Low-to-High transitions. Done Pin will have default 10Kohm resistor.

I belive connecting to VCCO_0 = 1.8V is recommeded and safe. Your condition is not charectrized by Xilinx.

Regards,

Deepak D N

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Please reply or give kudo or mark it as an Accepted Solution.

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Regards,
Deepak D N
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3 Replies
Xilinx Employee
Xilinx Employee
412 Views
Registered: ‎06-06-2018

Re: Ultrascale+ Maximum Configuration Bank 0 input voltage

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Hi @jsmithsrc,

Bank 0 are dedicated, you cannot change INIT_B and DONE pin voltage alone and the IO stanadard is also fixed i.e LVCMOS. Bank 0 get voltage based on VCCO_0 applied and CFVBGS pin. Please follow default Pull up.

Hope this cleares your query.

 

Regards,

Deepak D N

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Please reply or give kudo or mark it as an Accepted Solution.

--------------------------------------------------------------------------------------

Regards,
Deepak D N
---------------------------------------------------------------------------
Please Kudo and Accept as a Solution, If it helps.
---------------------------------------------------------------------------
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Adventurer
Adventurer
410 Views
Registered: ‎06-25-2012

Re: Ultrascale+ Maximum Configuration Bank 0 input voltage

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Sorry I wasn't clear.

If VCCO_0 is 1.8V, can I have pullups on INIT_B and DONE to 3.3?

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Xilinx Employee
Xilinx Employee
399 Views
Registered: ‎06-06-2018

Re: Ultrascale+ Maximum Configuration Bank 0 input voltage

Jump to solution

Hi @jsmithsrc,

INIT_B to a 4.7 kΩ pull-up resistor to VCCO_0 to ensure clean Low-to-High transitions. Done Pin will have default 10Kohm resistor.

I belive connecting to VCCO_0 = 1.8V is recommeded and safe. Your condition is not charectrized by Xilinx.

Regards,

Deepak D N

--------------------------------------------------------------------------------------

Please reply or give kudo or mark it as an Accepted Solution.

-------------------------------------------------------------------------------------

Regards,
Deepak D N
---------------------------------------------------------------------------
Please Kudo and Accept as a Solution, If it helps.
---------------------------------------------------------------------------

View solution in original post

0 Kudos