04-08-2021 02:10 AM
I am currently working on microZed, and I would like to externalize FPGA signals to zynq FPGA pins.
The thing is, most FPGA pins (bank 35) are differential ones, whereas my signals are not.
How should I deal with it ? Should I make my signals differential ?
Thanks for any help,
04-08-2021 02:20 AM
IO pins may be used for either differential or single ended signals. The names in the tables must reflect which pairs of pins need to be used for a differential signal.
04-08-2021 02:30 AM
The thing is, I only see two single-ended pins in bank 35 : JX2_SE_0, JX2_SE_1. (I may be wrong here)
I need more single-ended pins for all my fpga signals, how can I overcome that?