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Visitor luomsen
Visitor
437 Views
Registered: ‎06-26-2018

VU3P Configuration

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HI,

I have my VU3P design in Vivado Lab 2018.3.

Platform USB cable can find the FPGA device, but when I try to open Sysmon to monitor chip temp and VCCINT, it is not correct. the temp reads as -279, VCCINT as 0.0V.

Also I can't program device through JTAG.

The USB cable is OK as I verified. And FPGA JTAG port is directly connected to USB cable.

Vivado JTAG.png
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1 Solution

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Moderator
Moderator
301 Views
Registered: ‎06-05-2013

Re: VU3P Configuration

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Hi @luomsen

Can you confirm if Vivado is able to read the device properties? Refer to below snapshot. 

dajshhj.JPG

Try to read the configuration registers. 

Also what is the status of INIT_b when you are trying to program the device.

Can you probe INIT,PROG_b and CCLK.  

Thanks

Harshit

 

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3 Replies
Xilinx Employee
Xilinx Employee
403 Views
Registered: ‎06-06-2018

Re: VU3P Configuration

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Hi @luomsen,

1. FPGA full part number and Vivado version and OS details?

2. Are you using Custom board(please provide the schematic) or Xilinx board(specifyand share the snapshot of Power GOOD LEDS)?

3. Please ensure FPGA is voltage rails are fine. And also ensure there is no dip in the voltage rails. Please share the scopeshot of the all FPGA Voltage rails at power up and during detection of the board? and ensure that you are following the power sequence as provided by Xilinx.

4.JTAG FPGA detection: Please try reinstalling the USB drivers without reinstalling the Vivado by following this AR#59128.  And also try changing the cable also. 

5. when you connect the JTAG USB cable to the board, In device Manager in your PC/Laptop you were able to observe the Cable detection. Please share the snapshot(device manager(PORTS)) of the same?

 

Regards,

Deepak D N

 

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Visitor luomsen
Visitor
382 Views
Registered: ‎06-26-2018

Re: VU3P Configuration

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Hi @ddn

1. Full part number: XCVU3P-2FFVC1517E, Vivado is 2018.3, win10.

2. Customer board, schematic as attached.

3. Attached "Power Rails.png" shows all power rails, and looks good, no dip. And power up sequence as attached as "Power Sequence_1.png" and "Power Sequence_2.png", the difference between the two pictures is 1.2V and 1.8V power up order. both of the two configurations are not OK.

4. FPGA can be detected as shown in "JTAG_VU3P.png", the issue is that even though the JTAG can detect FPGA, but fail to get any information from the chip, like temp, VCCINT values, as the "JTAG_VU3P.png" picture shows.

5. JTAG cable is OK, the device manage show as "XlinxUSBCabel.png". And I can use the same cable and same Vivado to get 325T FPGA chip, as shown in picture as "JTAG_325T.png"

Please check these info and your suggestions will be appreciated.

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Moderator
Moderator
302 Views
Registered: ‎06-05-2013

Re: VU3P Configuration

Jump to solution

Hi @luomsen

Can you confirm if Vivado is able to read the device properties? Refer to below snapshot. 

dajshhj.JPG

Try to read the configuration registers. 

Also what is the status of INIT_b when you are trying to program the device.

Can you probe INIT,PROG_b and CCLK.  

Thanks

Harshit

 

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Don’t forget to reply, kudo, and accept as solution.
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