01-14-2020 04:17 AM
We have a circuit board where we use the Virtex-7 XC7K410T together with a quad SPI flash FPGA configuration memory of the type MT25QU512. The Flash is programmed with a program and the FPGA boots as intended when we wish to do so. In order to prevent the FPGA from booting we pull the INIT_B pin low.
In order to test the board we use JTAG Provision in order to run Boundary Scan tests (such as pull up/down, bridge, walking etc). However, we experience that the FPGA starts booting from the Flash during the Boundary Scan tests, even if the INIT_B pin is pulled LOW with a jumper directly on the circuit board.
We have been in contact with the JTAG Provision support group, and they made us configure Provision so that the INIT_B pin is "Assumed 0". Still the FPGA booted during Boundary Scan testing. Next they recommended we also pull the PROGRAM_B pin low in order to prevent the FPGA from booting. This appears to work, but according to UG470 - 7 Series FPGAs Configuration User Guide on page 25: "Note: Holding PROGRAM_B Low from power-on does notkeep the FPGA configuration in reset. Instead, use INIT_B to delay the power-on configuration sequence." However it appears that only holding the INIT_B pin low does not prevent the FPGA from booting. Both INIT_B and PROGRAM_B has a pullup resistor to VCC.
So our questions are;
Is holding the PROGRAM_B and the INIT_B pin a safe way to prevent the FPGA from booting during Boundary Scan testing? Are there other ways we can prevent the FPGA from booting while running boundary scan tests? Has anyone else had experience with their FPGA booting unintentionally while running Boundary Scan tests?
HW Development Engineer
01-14-2020 07:12 PM
Do you mean the FPGA start booting even if you hold INIT_B and PROG_B low? That sounds impossible.
Anyhow, set the mode pins to 111 or 101. This will prevent the FPGA boot from flash.