Vivado 2020.1 Sythesis probelm

[RRN1]

I have a simple inverter before a register in VHDL that is shown correctly in RTL Analysis schematic but when implemented, is totally ignored.  This is preventing some of my logic from coming out of reset.  I know the clock is working since my LEDs flash from a register clocked by this and I know the system reset is released for the same reason.  This leaves just the inverter.  I know it is not implemented because I monitored the input and output signals with an ILA.  The output = input which is wrong.  I have attached screen captures to clarify the issue.  The VHDL show the source process, the Elaborated Schematic shows the correctly inferred logic, the Synthesis shows FDRE with a hint of an inverter in the cell name (isys_s2mm_reset_s_reg_inv), the Implementation schematic shows the same as the Synthesis schematic.  The Hardware Manager ILA capture clearly shows isys_mm2s_reset_s <= mm2s_prmry_reset_out_n_0 when isysrst99m99_s (active-high system reset) is released.  This is wrong, it should be isys_mm2s_reset_s <= NOT mm2s_prmry_reset_out_n_0

Does anyone know of a setting that could cause this?  Is this a bug in the tools?

Hope someone can help.  Thank you.

[yannickl]

Hi,

Looking at the generated cells, your register was also changed from FDSE to FDRE. I'd assume this optimization was done to better pack the registers in a slice and I'd bet the inverting equivalent logic happens on the reset net.

Also, don't go looking for a NOT cell. After synthesis (or within Vivado the implicit step of tech mapping) it won't exist anymore. FPGAs use LUTs.

Regards,

YL

[RRN1 · Accepted solution]

Thank you for the reply.  I was debugging why my MCDMA was not working when I noticed that my resets weren't what I expected them to be and so I came across this behavior which threw me.  Of course on closer inspection, I used the wrong polarity reset further down the line so I suspect a different reason for my design not coming out of reset.  Happy debug days!  Thanks again.