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Observer
Observer
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Registered: ‎07-18-2013

Workaround for FPGA_DONE pin connecting to GND ?

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Dear all,

We have this custom board somehow with this mistake. The done pin is connected directly to the GND, no resistor in between.

of course we had this error after programing the device through JTAG. which is "End of startup status: LOW"

I have tried the settings->bitstream->startup->"wait on the done pin to go high" to a NO. 

I got the same error, but the FPGA seemed to be programmed succesfully. 

The problem is, with this error, I can not get to the debug UI. Hope somebody can help us to further bypass the error.

 

Best regards.

Bing

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Xilinx Employee
Xilinx Employee
461 Views
Registered: ‎08-10-2008

I'm afraid there is no way to work around this. 

Internal Config logic relies on the detection of this pin for a HIGH voltage and then it continues the Startup phase. If it detects a LOW, it simply stops.

You must cut off the trace between DONE and GND ( if you could). Then you can use bitstream setting 'drive DONE pin high' , drive from internal logic to make FPGA work. No need to add an external pullup.

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Xilinx Employee
Xilinx Employee
462 Views
Registered: ‎08-10-2008

I'm afraid there is no way to work around this. 

Internal Config logic relies on the detection of this pin for a HIGH voltage and then it continues the Startup phase. If it detects a LOW, it simply stops.

You must cut off the trace between DONE and GND ( if you could). Then you can use bitstream setting 'drive DONE pin high' , drive from internal logic to make FPGA work. No need to add an external pullup.

------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------

View solution in original post

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Observer
Observer
451 Views
Registered: ‎07-18-2013

Thanks. 

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