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bhavyamadan@lft
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Registered: ‎06-07-2017

ZCU102 - The debug hub core was not detected.

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Hi,

I have recently acquired a ZCU102(IDCODE = 1) evaluation board, and using Vivado SDK 2017.1 for configuration file generation.

 

When I try to program my board, I get this error

Incorrect bitstream assigned to device. Bitstream was generated for part xczu9eg-ffvb1156-2-i, target device (with IDCODE revision 1) is compatible with es2 revision bitstreams.

So using "set_param xicom.use_bitstream_version_check false" tcl command this error is downgraded to a warning.

 

After this I am able to program the bitfile and init_done LED also illuminates, but the Vivado hardware manager is unable to detect the debug_hub, giving this warning 

WARNING: [Labtools 27-3361] The debug hub core was not detected.

WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xczu9_0 and the probes file(s) 

                   The device design has 0 ILA core(s) and 0 VIO core(s). The probes file(s) have 2 ILA core(s) and 3 VIO core(s).

 

According to AR# 58406, following are possible fixes for this error:

  • Ensure that the .bit file and the .ltx file assigned to this device match each other.
  • Ensure that the capture clock to the ILA is a free running clock
  • Ensure that timing requirement has been met after inserting Debug cores.
  • The error can be caused by a Signal Integrity issue on the board.
    A case was found where the issue was caused by a bad USB Cable.
  • In one case creating a new project resolved the error.
  • Ensure that the Version of the core matches the version of the tools, and hw_manager.

But none of it worked for me.

Can anyone please point out why it might be happening or what can I do.

PS: I have checked the same RTL code for VCU110, It is working fine.

 

Thanks 

Bhavya Madan

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bhavyamadan@lft
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Registered: ‎06-07-2017

Hi @florentw

The issue was the GTH core was not receiving the reference clock from the board and there is an ILA, captures the rx and tx data, in my design which is using rx_usrclk2 and tx_userclk2 (both generated by the GTH core). Hence the debug_hub was not detected.

 

To support my finding, I added a VIO block and clock counter to my design, to check if the clocks are generated by the core, the output of clock both the usrclk2 was zero. Furthermore I changed the GTH quad from bank 129 to 130 and the same design worked just fine.

 

PS: Quad 129 used USER_MGT_SI570_CLOCK1 as reference clock 

       Quad 130 used FMC_HPC1_GBTCLK0/1_M2C as reference clock

       For more details look at UG1182(ZCU102 Evaluation Board), page 80

 

Regards 

Bhavya Madan

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dpaul24
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Registered: ‎08-07-2014

I am not sure if this would work....

 

Re-generate the output products ILA/VIO cores and then generate the bitstream.

 

When I try to program my board, I get this error

Incorrect bitstream assigned to device. Bitstream was generated for part xczu9eg-ffvb1156-2-i, target device (with IDCODE revision 1) is compatible with es2 revision bitstreams.

So using "set_param xicom.use_bitstream_version_check false" tcl command this error is downgraded to a warning.

 

Also it is not a nice thing to ignore this. It is good to update your project for the device your board supports. Upgrade any IP that requires an upgrade. Then generate a fresh bit stream and run it on your board.

------------FPGA enthusiast------------
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bhavyamadan@lft
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Registered: ‎06-07-2017

Hi @dpaul24

All the ILAs and VIOs are up to date, I am not using an imported project.

I have selected the board ZCU102 rev 1.0 in Vivado, which is the board I am using. 

 

I have downgraded the error message because doing this is been marked as a solution in this thread below

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Bitstream-is-not-compatible-while-programming-FPGA/td-p/782150

 

Regards

Bhavya Madan

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florentw
Moderator
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Registered: ‎11-09-2015

Hi bhavyamadan@lft,

 

What is the status of this issue?

 

Just back to this thread:

-> For the ILA issue: make sure the PS is up and running (start an application in SDK) because the ILA is using the clocks for the PS

 

-> For the bitstream incompatible: The rev-1 board can have a production silicon or an engineering sample (ES2). There should be 2 different board in vivado corresponding to the 2 different silicon. Make sure to select the correct one.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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bhavyamadan@lft
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Registered: ‎06-07-2017

Hi @florentw

The issue was the GTH core was not receiving the reference clock from the board and there is an ILA, captures the rx and tx data, in my design which is using rx_usrclk2 and tx_userclk2 (both generated by the GTH core). Hence the debug_hub was not detected.

 

To support my finding, I added a VIO block and clock counter to my design, to check if the clocks are generated by the core, the output of clock both the usrclk2 was zero. Furthermore I changed the GTH quad from bank 129 to 130 and the same design worked just fine.

 

PS: Quad 129 used USER_MGT_SI570_CLOCK1 as reference clock 

       Quad 130 used FMC_HPC1_GBTCLK0/1_M2C as reference clock

       For more details look at UG1182(ZCU102 Evaluation Board), page 80

 

Regards 

Bhavya Madan

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