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krn-krn
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Registered: ‎12-17-2019

booting from configuration memory device unsuccessful

Hi.

i am using spartan 7 fpga ,and  i am programming  s25fl128sagnfi000 flash  ,flash programming successfuly,but booting from the configuration memory device unsuccessfull,how do i boot successfully.

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wduffy
Xilinx Employee
Xilinx Employee
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Registered: ‎01-21-2013

Hi @krn-krn,

 

What version of the Vivado tool are you using?

Can you post the error message you see when you fail to boot the FPGA from the flash?

Can you also post the full output from the console window in Vivado?

How have you attempted to boot the FPGA from the flash e.g. power cycled the board, used the “Boot from Configuration Memory Device” option in Vivado?

Capture.PNG

 

Thanks,
Wendy
Xilinx Technical Support
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krn-krn
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create_project s_0_flash C:/Users/lenovo/projects/s_0_flash -part xc7s50fgga484-2
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
create_project: Time (s): cpu = 00:01:36 ; elapsed = 00:00:49 . Memory (MB): peak = 808.512 ; gain = 21.145
file mkdir C:/Users/lenovo/projects/s_0_flash/s_0_flash.srcs/sources_1/new
close [ open C:/Users/lenovo/projects/s_0_flash/s_0_flash.srcs/sources_1/new/s_o_rtl.v w ]
add_files C:/Users/lenovo/projects/s_0_flash/s_0_flash.srcs/sources_1/new/s_o_rtl.v
update_compile_order -fileset sources_1
launch_runs synth_1 -jobs 4
[Mon Jun 15 12:48:17 2020] Launched synth_1...
Run output will be captured here: C:/Users/lenovo/projects/s_0_flash/s_0_flash.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 829.875 ; gain = 12.781
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7s50fgga484-2
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7s50fgga484-2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

open_run: Time (s): cpu = 00:01:52 ; elapsed = 00:01:11 . Memory (MB): peak = 1192.109 ; gain = 360.867
place_ports y T19
set_property IOSTANDARD LVCMOS33 [get_ports [list y]]
file mkdir C:/Users/lenovo/projects/s_0_flash/s_0_flash.srcs/constrs_1/new
close [ open C:/Users/lenovo/projects/s_0_flash/s_0_flash.srcs/constrs_1/new/cc.xdc w ]
add_files -fileset constrs_1 C:/Users/lenovo/projects/s_0_flash/s_0_flash.srcs/constrs_1/new/cc.xdc
set_property target_constrs_file C:/Users/lenovo/projects/s_0_flash/s_0_flash.srcs/constrs_1/new/cc.xdc [current_fileset -constrset]
save_constraints -force
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
[Mon Jun 15 14:44:31 2020] Launched synth_1...
Run output will be captured here: C:/Users/lenovo/projects/s_0_flash/s_0_flash.runs/synth_1/runme.log
[Mon Jun 15 14:44:32 2020] Launched impl_1...
Run output will be captured here: C:/Users/lenovo/projects/s_0_flash/s_0_flash.runs/impl_1/runme.log
startgroup
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [get_designs synth_1]
set_property config_mode SPIx1 [current_design]
endgroup
write_cfgmem -format mcs -size 128 -interface SPIx1 -loadbit {up 0x00000000 "C:/Users/lenovo/projects/s_0_flash/s_0_flash.runs/impl_1/s_o_rtl.bit" } -file "C:/Users/lenovo/AppData/Roaming/Xilinx/Vivado/x_f_procedure.mcs"
Command: write_cfgmem -format mcs -size 128 -interface SPIx1 -loadbit {up 0x00000000 "C:/Users/lenovo/projects/s_0_flash/s_0_flash.runs/impl_1/s_o_rtl.bit" } -file C:/Users/lenovo/AppData/Roaming/Xilinx/Vivado/x_f_procedure.mcs
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile C:/Users/lenovo/projects/s_0_flash/s_0_flash.runs/impl_1/s_o_rtl.bit
Writing file C:/Users/lenovo/AppData/Roaming/Xilinx/Vivado/x_f_procedure.mcs
Writing log file C:/Users/lenovo/AppData/Roaming/Xilinx/Vivado/x_f_procedure.prm
===================================
Configuration Memory information
===================================
File Format MCS
Interface SPIX1
Size 128M
Start Address 0x00000000
End Address 0x07FFFFFF

Addr1 Addr2 Date File(s)
0x00000000 0x0021728B Jun 15 15:00:30 2020 C:/Users/lenovo/projects/s_0_flash/s_0_flash.runs/impl_1/s_o_rtl.bit
0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
write_cfgmem: Time (s): cpu = 00:00:29 ; elapsed = 00:00:19 . Memory (MB): peak = 2334.105 ; gain = 171.852
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


connect_hw_server: Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 2334.105 ; gain = 0.000
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/00001b3b813e01
set_property PROGRAM.FILE {C:/Users/lenovo/projects/s_0_flash/s_0_flash.runs/impl_1/s_o_rtl.bit} [get_hw_devices xc7s50_0]
current_hw_device [get_hw_devices xc7s50_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7s50_0] 0]
INFO: [Labtools 27-1434] Device xc7s50 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
create_hw_cfgmem -hw_device [lindex [get_hw_devices xc7s50_0] 0] [lindex [get_cfgmem_parts {s25fl128sxxxxxx0-spi-x1_x2_x4}] 0]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
refresh_hw_device [lindex [get_hw_devices xc7s50_0] 0]
INFO: [Labtools 27-1434] Device xc7s50 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.FILES [list "C:/Users/lenovo/AppData/Roaming/Xilinx/Vivado/x_f_procedure.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.PRM_FILES [list "C:/Users/lenovo/AppData/Roaming/Xilinx/Vivado/x_f_procedure.prm" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.FILES [list "C:/Users/lenovo/AppData/Roaming/Xilinx/Vivado/x_f_procedure.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.PRM_FILE {C:/Users/lenovo/AppData/Roaming/Xilinx/Vivado/x_f_procedure.prm} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
startgroup
if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices xc7s50_0] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices xc7s50_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xc7s50_0] 0]]; program_hw_devices [lindex [get_hw_devices xc7s50_0] 0]; };
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0
Performing Erase Operation...
Erase Operation successful.
Performing Program and Verify Operations...
Program/Verify Operation successful.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:06 ; elapsed = 00:02:25 . Memory (MB): peak = 2334.105 ; gain = 0.000
endgroup
boot_hw_device [lindex [get_hw_devices xc7s50_0] 0]
INFO: [Labtoolstcl 44-664] Will wait up to 180 seconds for booting to complete.
ERROR: [Labtools 27-2254] Booting from configuration memory device unsuccessful.
boot_hw_device: Time (s): cpu = 00:00:03 ; elapsed = 00:03:01 . Memory (MB): peak = 2334.105 ; gain = 0.000
ERROR: [Common 17-39] 'boot_hw_device' failed due to earlier errors.

i am using vivado 2014.4
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krn-krn
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Registered: ‎12-17-2019

I have used "Boot from Configuration Device" option to Boot the device.
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krn-krn
Adventurer
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Registered: ‎12-17-2019

sorry, i am using vivado 2017.4

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wduffy
Xilinx Employee
Xilinx Employee
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Registered: ‎01-21-2013

Hi @krn-krn

 

What version of tool did you generate the bitstream in for the Spartan-7 device?

You mentioned 2014.4. However, I don’t believe Spartan-7 was supported in 2014.4.

Can you provide the output of the status registers also from Vivado?

 

Thanks,
Wendy
Xilinx Technical Support
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krn-krn
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by mistakenly i typed 2014.4, i m using 2017.4
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krn-krn
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Registered: ‎12-17-2019

Screenshot (5).pngScreenshot (6).pngScreenshot (7).pngScreenshot (8).pngScreenshot (9).png

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krn-krn
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Registered: ‎12-17-2019

even i tried M[2:0]=001 but if do change also its automatically taking 111 how to fix this.

or i am missing anything please help me. 

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wduffy
Xilinx Employee
Xilinx Employee
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Registered: ‎01-21-2013

Hi @krn-krn,

 

Can you refresh the device in Vivado by right-clicking the FPGA and hitting “Refresh Device” and then read the status registers (similar to the below screenshot)?

forum_post.png

Can you also share configuration part of your schematic?

 

 

Thanks,
Wendy
Xilinx Technical Support
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krn-krn
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Registered: ‎12-17-2019

problem was in our custome board schematic,we rectified that,thank you.
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vishnu.k
Contributor
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Registered: ‎07-24-2018

Hi @wduffy 

I am using Zynq+ MPSoc.

I am getting this error when using the option "Boot from configuration memory device".

INFO: [Labtools 27-1435] Device xczu21dr (JTAG device index = 2) is not programmed (DONE status = 0).
current_hw_device [get_hw_devices arm_dap_3]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_3] 0]
current_hw_device [get_hw_devices xczu21dr_2]
boot_hw_device [lindex [get_hw_devices xczu19_0] 0]
INFO: [Labtoolstcl 44-664] Will wait up to 180 seconds for booting to complete.
CRITICAL WARNING: [Xicom 50-185] Defaulting to hardware boot mode: JTAG. Reset will have no effect.
INFO: [Labtools 27-2278] Device boot from configuration memory successful
refresh_hw_device [lindex [get_hw_devices xczu19_0] 0]
CRITICAL WARNING: [Labtools 27-3421] xczu19_0 PL Power Status OFF, cannot connect PL TAP. Check POR_B signal.
INFO: [Labtools 27-1435] Device xczu19 (JTAG device index = 0) is not programmed (DONE status = 0).
boot_hw_device [lindex [get_hw_devices xczu19_0] 0]
INFO: [Labtoolstcl 44-664] Will wait up to 180 seconds for booting to complete.
CRITICAL WARNING: [Xicom 50-185] Defaulting to hardware boot mode: JTAG. Reset will have no effect.
INFO: [Labtools 27-2278] Device boot from configuration memory successful
refresh_hw_device [lindex [get_hw_devices xczu19_0] 0]
CRITICAL WARNING: [Labtools 27-3421] xczu19_0 PL Power Status OFF, cannot connect PL TAP. Check POR_B signal.
INFO: [Labtools 27-1435] Device xczu19 (JTAG device index = 0) is not programmed (DONE status = 0).
boot_hw_device [lindex [get_hw_devices xczu19_0] 0]
INFO: [Labtoolstcl 44-664] Will wait up to 180 seconds for booting to complete.
CRITICAL WARNING: [Xicom 50-185] Defaulting to hardware boot mode: JTAG. Reset will have no effect.
INFO: [Labtools 27-2278] Device boot from configuration memory successful
refresh_hw_device [lindex [get_hw_devices xczu19_0] 0]
CRITICAL WARNING: [Labtools 27-3421] xczu19_0 PL Power Status OFF, cannot connect PL TAP. Check POR_B signal.
INFO: [Labtools 27-1435] Device xczu19 (JTAG device index = 0) is not programmed (DONE status = 0).

 

What I'm doing is, 

Power on the board in JTAG mode. Then changed the mode to QSPI.

Added configuration memory and did option "Boot from configuration memory device".

Did this several times but the same error happens. Am I doing anything wrong?

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