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Visitor
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Registered: ‎10-17-2018

reached max DSP utilization move to logic implementation

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Hi,

 

i am design a matrix of MACs unit using the IP core already provided however when i increase the size of the matrix, reaching the maximum number of DSPs in my board (220, it is the Zynq7000) i have an implementation error because the required DSP unit are bigger than the available ones.

Is there any way to force (or instruct) Vivado in order to start to use programmable logic as soon as the maximum number of available DSP is reached?
I modified the max_dsp parameter for the synthesis  moving to -1, which allows to use the maximum available number of dsp to the effective number of available dsp for the IC, 220. However it didn't change anything.

The board  is the PYNQ Z2 from Tul.

 

 

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Scholar
Scholar
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Registered: ‎05-21-2015

@ffran,

To be clear then, the answer to the question of whether or not the tool will automatically generate fabric DSP logic is .... No.

There is no fabric multiplier logic that is or even could be equivalent to the timing of a DSP.  (Trust me, I've tried.)  The engineer is required to get involved in order to create an appropriate multiply, and to properly adjust his design so that it now interfaces with any such fabric implementation.

Dan

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Scholar
Scholar
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Registered: ‎05-21-2015

@ffran,

If you swap a DSP element doing an 18x18 multiply for fabric logic, you will need to restrict your speed so much that it would've made more sense to multiplex the DSP's instead.  As a result, this isn't really a practical solution to running out of DSPs.

Better solutions might be to ...

  • Raise your clock speed to the absolute maximum, and tune the rest of your logic to handle it.  You'll need to make sure you are feeding your multiplies at high speed as well, so that's another issue
  • Multiplex the DSPs to the point where every DSP is being used on every clock cycle.  Indeed, if you aren't using every DSP on every clock cycle, then that's probably where you should first focus your efforts.

Dan

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Visitor
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Registered: ‎10-17-2018

hi

my rtl is a data flow architecture of for example a 8x8 matrix of MACs (each one of them multiplys and acccumulates on 8 bits)  however if i increase the size of the matrix reaching the maximum number of dsp hard fabric (220 in my case) i got an error from the implementation.

I totally understand the implementaiton error, i cannot use something that's not there.

Anyway my question was is there any way to start to implement the DSP function in logic as soon as we run out of DSP cores?

 

FFran

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Scholar
Scholar
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Registered: ‎05-21-2015

@ffran,

To be clear then, the answer to the question of whether or not the tool will automatically generate fabric DSP logic is .... No.

There is no fabric multiplier logic that is or even could be equivalent to the timing of a DSP.  (Trust me, I've tried.)  The engineer is required to get involved in order to create an appropriate multiply, and to properly adjust his design so that it now interfaces with any such fabric implementation.

Dan

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