cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
victord
Observer
Observer
732 Views
Registered: ‎01-25-2021

reboot failure using icap process

Jump to solution

Hello , I created a simple design for testing the reboot process using IPROG command.


I built 2 basic designs (golden and silver)  with the same architecture ( toggle output led).

the difference between them are:

1) the constraints file are different - the output led is different in the evaluation board I used ( AC701 with artix 7)

2)the reboot process included only in the golden design

note: all the project files are attached

 

the reboot strobe is controlled by an evaluation board dip switch which connected to the fpga target.

the new boot address is the address of the silver design.

however, after programming the flash and pushing the switch to reboot, I do not get the expected results and the loaded design is the golden once again after a few seconds in some act of fallback maybe.

I attached here all the project files I used.

can you please guide me to find the mistake ?

thank you very much for your help!!


Victor

 
0 Kudos
Reply
1 Solution

Accepted Solutions
miker
Xilinx Employee
Xilinx Employee
217 Views
Registered: ‎11-30-2007

@victord 

I have attached 3 Vivado 2020.2 projects:  golden, silver, and bronze.

I took your code and created a design that will load silver by default and then allow a multiboot jump to bronze.  The bronze allows a multiboot jump back to silver.

SW2:1 DIP > Issues IPROG (Active High)
SW3 PB    > Reset

GPIO_0 '1' > Golden loaded
GPIO_2 '1' > Bronze loaded
GPIO_3 '1' > Silver loaded (default boot)

Golden ... 0x0000_0000
Silver ... 0x0100_0000 (default boot)
Bronze ... 0x0180_0000

To create full Golden+Silver+Bronze MCS:
write_cfgmem -format mcs -size 32 -interface SPIx1 -loadbit {up 0x00000000 "<path>/golden/golden.runs/impl_1/ver1_top.bit" up 0x01000000 "<path>/silver/silver.runs/impl_1/ver2_top.bit" up 0x01800000 "<path>/bronze/bronze.runs/impl_1/ver3_top.bit" } -file "<path>/combined_timer.mcs"

To create only Golden+Silver (to see Golden load)
write_cfgmem -format mcs -size 32 -interface SPIx1 -loadbit {up 0x00000000 "<path>/golden/golden.runs/impl_1/ver1_top.bit" up 0x01000000 "<path>/silver/silver.runs/impl_1/ver2_top.bit" } -file "<path>/golden_silver_timer.mcs"

When programming the AC701 SPI Flash, be sure to Program/Erase/Verify the Address RangeEntire Configuration Memory Device (versus Configuration File Only) to make sure you clear the entire Flash PROM.

forums_7series_golden_fallback_mcs.png

If you program the combined_timer.mcs, you will see the Silver configure by default (GPIO_3 LED on).  You can issue an IPROG by toggling SW2:1 up-then-down and you will see Bronze configure (GPIO_2 LED on).  You can issue an IPROG by toggling SW2:1 up-then-down and you will see Silver configure (GPIO_3 LED on).  And this continues.

If you program the golden_silver_timer.mcs, you will see the Silver configure by default (GPIO_3 LED on).  You can issue an IPROG by toggling SW2:1 up-then-down ... now wait a little time ... and you will see Golden configure (GPIO_0 LED on).  This is in the fallback state.  You can exit the Golden fallback state by issuing an IPROG by toggling SW2:1 up-then-down and you will see Silver configure (GPIO_3 LED on).

I hope this helps.

Please Reply, Kudos, and Accept as Solution.

View solution in original post

9 Replies
miker
Xilinx Employee
Xilinx Employee
703 Views
Registered: ‎11-30-2007

@victord 

Did you reference the MultiBoot with 7 Series FPGAs and SPI Application Note (XAPP1247; v1.1)?

I reviewed your XDC files for both the Golden and Silver designs but did not see the MultiBoot Bitstream Properties required for each (reference Table 1: MultiBoot Bitstream Properties) :

forums_xapp1247_tabl1.png

These are the XDC constraints required for the golden design.  Please note the BITSTREAM.CONFIG.NEXT_CONFIG_ADDR value is design dependent.

forums_xapp1247_golden.png

These are the XDC constraints required for the silver design.

forums_xapp1247_silver.png

Please Reply, Kudos, and Accept as Solution.
miker
Xilinx Employee
Xilinx Employee
608 Views
Registered: ‎11-30-2007

@victord 

Did my reply to your post resolve your issue? If so, please select Accept as Solution so that others may benefit from your experience. If you found the reply helpful, please also provide a Kudos.  Thank you.

Please Reply, Kudos, and Accept as Solution.
0 Kudos
Reply
victord
Observer
Observer
552 Views
Registered: ‎01-25-2021

Hi Miker,

thank you again for your quick response,

your reply hasn't solved my issue yet.

I attached the updated constraints files with rest of design files.


Additionally, I uploaded th tcl commands i used to create the mcs file and the hardware manager configurations i used to program the flash .


I am using the ac701 evaluation board for the artix 7 target , after programming the flash memory, I turned off  the device and the jtag connection .then powered up the device and none of the design files are active( golden or silver) , moreover , DS1 led is red instead of green ( which I think indicates that there is a problem with the configuration maybe).

Can you suggest how to solve this case ?

thank you very much Miker.

 

 

 

 

0 Kudos
Reply
victord
Observer
Observer
552 Views
Registered: ‎01-25-2021

** attached tcl command and hardware manager window **

0 Kudos
Reply
miker
Xilinx Employee
Xilinx Employee
419 Views
Registered: ‎11-30-2007

@victord 

I noticed in your constraints files that you misspelled BITSTREAM on the line for the BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE.  You also missed the underscore in current_design and instead inserted a space.

If this doesn't work, I noticed you are targeting a 256Mb Flash yet you specified a size of 128Mb.  You may need to accommodate for SPI 32-bit Addressing.  You can reference the 7 Series FPGAs Configuration User Guide (UG470; v1.13.1) regarding SPI 32-bit addressing mode.

For SPI 32-bit addressing mode, WBSTAR[23:0] are sent as address bits [31:8]. The lower 8 bits of the address are undefined and the value could be as high as 0xFF. Any bitstream at the WBSTAR address should contain 256 dummy bytes before the start of the bitstream.

forums_multiboot__golden_xdc.png

forums_multiboot__silver_xdc.png

 

 

Please Reply, Kudos, and Accept as Solution.
victord
Observer
Observer
235 Views
Registered: ‎01-25-2021

HI miker, thank you again for your response .

I fixed the errors you mentioned ( Specified size of 256M  and other spelling errors)

In addition ,I changed the WBSTAR address according to the user guide .

I am using the ac701 evaluation board for the artix 7 target , after programming the flash memory, I turned off  the device and the jtag connection .then powered up the device and none of the design files are active( golden or silver) , moreover , DS1 led is red instead of green ( which I think indicates that there is a problem with the configuration maybe).

I think that my mistake is still somewhere in the address configuration, so i want to make it clear .

there are 3 places where the WBSTAR should be written:

1) in the tcl command to create the flash .mcs file

2) in the next address constraint

3)in the reboot .vhd inside the IPROG command 

The NEXT address I chose for this project is 0x1000000. I wrote this address inside the constraint file and the tcl command.

but,  as Inside the reboot IPROG command process, all the data is "flipped" so instead sending 0x1000000 i send 0x080000. MOREOVER ,after your last answer, the user guide tells us to send only the 24 MSBits of WBSTR so instead sending 0x080000 i send 0x00008000.

To sum up the addressing i used :

1)the tcl cmd and constraint used the address :0x1000000

2) the reboot process used the address :0x00008000

is this the correct method ?

If not , what std_logic_vector should I send during the reboot process to WBSTAR cmd.

If yes, what could be the reason for this design not to work properly ? each one of the bitstream works good seperately.

 

Thank you milker.

0 Kudos
Reply
miker
Xilinx Employee
Xilinx Employee
218 Views
Registered: ‎11-30-2007

@victord 

I have attached 3 Vivado 2020.2 projects:  golden, silver, and bronze.

I took your code and created a design that will load silver by default and then allow a multiboot jump to bronze.  The bronze allows a multiboot jump back to silver.

SW2:1 DIP > Issues IPROG (Active High)
SW3 PB    > Reset

GPIO_0 '1' > Golden loaded
GPIO_2 '1' > Bronze loaded
GPIO_3 '1' > Silver loaded (default boot)

Golden ... 0x0000_0000
Silver ... 0x0100_0000 (default boot)
Bronze ... 0x0180_0000

To create full Golden+Silver+Bronze MCS:
write_cfgmem -format mcs -size 32 -interface SPIx1 -loadbit {up 0x00000000 "<path>/golden/golden.runs/impl_1/ver1_top.bit" up 0x01000000 "<path>/silver/silver.runs/impl_1/ver2_top.bit" up 0x01800000 "<path>/bronze/bronze.runs/impl_1/ver3_top.bit" } -file "<path>/combined_timer.mcs"

To create only Golden+Silver (to see Golden load)
write_cfgmem -format mcs -size 32 -interface SPIx1 -loadbit {up 0x00000000 "<path>/golden/golden.runs/impl_1/ver1_top.bit" up 0x01000000 "<path>/silver/silver.runs/impl_1/ver2_top.bit" } -file "<path>/golden_silver_timer.mcs"

When programming the AC701 SPI Flash, be sure to Program/Erase/Verify the Address RangeEntire Configuration Memory Device (versus Configuration File Only) to make sure you clear the entire Flash PROM.

forums_7series_golden_fallback_mcs.png

If you program the combined_timer.mcs, you will see the Silver configure by default (GPIO_3 LED on).  You can issue an IPROG by toggling SW2:1 up-then-down and you will see Bronze configure (GPIO_2 LED on).  You can issue an IPROG by toggling SW2:1 up-then-down and you will see Silver configure (GPIO_3 LED on).  And this continues.

If you program the golden_silver_timer.mcs, you will see the Silver configure by default (GPIO_3 LED on).  You can issue an IPROG by toggling SW2:1 up-then-down ... now wait a little time ... and you will see Golden configure (GPIO_0 LED on).  This is in the fallback state.  You can exit the Golden fallback state by issuing an IPROG by toggling SW2:1 up-then-down and you will see Silver configure (GPIO_3 LED on).

I hope this helps.

Please Reply, Kudos, and Accept as Solution.

View solution in original post

miker
Xilinx Employee
Xilinx Employee
212 Views
Registered: ‎11-30-2007

@victord 

I will highlight the 3 XDC file contents below for quick reference:

golden_constraints.xdc

set_property CONFIG_VOLTAGE {3.3} [current_design]
set_property CFGBVS         VCCO  [current_design]
set_property CONFIG_MODE    SPIx1 [current_design]

set_property -dict { PACKAGE_PIN M26 IOSTANDARD LVCMOS33 }    [get_ports LED]
set_property -dict { PACKAGE_PIN T24 IOSTANDARD LVCMOS33 }    [get_ports REBOOT_STATUS]
set_property -dict { PACKAGE_PIN R8  IOSTANDARD LVCMOS15 }    [get_ports REBOOT]
set_property -dict { PACKAGE_PIN P6  IOSTANDARD LVCMOS15 }    [get_ports RESET]
set_property -dict { PACKAGE_PIN R3  IOSTANDARD DIFF_SSTL15 } [get_ports CLK_IN1_P]
set_property -dict { PACKAGE_PIN P3  IOSTANDARD DIFF_SSTL15 } [get_ports CLK_IN1_N]

set_property BITSTREAM.CONFIG.CONFIGFALLBACK   ENABLE       [current_design]
set_property BITSTREAM.GENERAL.COMPRESS        TRUE         [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH     1            [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR   Yes          [current_design]
set_property BITSTREAM.CONFIG.TIMER_USR        32'h402FAF08 [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 32'h01000000 [current_design]

silver_constraints.xdc

set_property CONFIG_VOLTAGE {3.3} [current_design]
set_property CFGBVS         VCCO  [current_design]
set_property CONFIG_MODE    SPIx1 [current_design]

set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33    } [get_ports LED]
set_property -dict { PACKAGE_PIN T24 IOSTANDARD LVCMOS33    } [get_ports REBOOT_STATUS]
set_property -dict { PACKAGE_PIN R8  IOSTANDARD LVCMOS15    } [get_ports REBOOT]
set_property -dict { PACKAGE_PIN P6  IOSTANDARD LVCMOS15    } [get_ports RESET]
set_property -dict { PACKAGE_PIN R3  IOSTANDARD DIFF_SSTL15 } [get_ports CLK_IN1_P]
set_property -dict { PACKAGE_PIN P3  IOSTANDARD DIFF_SSTL15 } [get_ports CLK_IN1_N]

set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE       [current_design]
set_property BITSTREAM.GENERAL.COMPRESS      TRUE         [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH   1            [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes          [current_design]
set_property BITSTREAM.CONFIG.TIMER_USR      32'h402FAF08 [current_design]

bronze_constraints.xdc

set_property CONFIG_VOLTAGE {3.3} [current_design]
set_property CFGBVS         VCCO  [current_design]
set_property CONFIG_MODE    SPIx1 [current_design]

set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33    } [get_ports LED]
set_property -dict { PACKAGE_PIN T24 IOSTANDARD LVCMOS33    } [get_ports REBOOT_STATUS]
set_property -dict { PACKAGE_PIN R8  IOSTANDARD LVCMOS15    } [get_ports REBOOT]
set_property -dict { PACKAGE_PIN P6  IOSTANDARD LVCMOS15    } [get_ports RESET]
set_property -dict { PACKAGE_PIN R3  IOSTANDARD DIFF_SSTL15 } [get_ports CLK_IN1_P]
set_property -dict { PACKAGE_PIN P3  IOSTANDARD DIFF_SSTL15 } [get_ports CLK_IN1_N]

set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE       [current_design]
set_property BITSTREAM.GENERAL.COMPRESS      TRUE         [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH   1            [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes          [current_design]
set_property BITSTREAM.CONFIG.TIMER_USR      32'h402FAF08 [current_design]

 

Please Reply, Kudos, and Accept as Solution.
0 Kudos
Reply
victord
Observer
Observer
56 Views
Registered: ‎01-25-2021

Thank you Miker, It solved my issue

0 Kudos
Reply