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Visitor
Visitor
533 Views
Registered: ‎07-01-2018

spartan3 an program error

Hi dears,

I have a board with spartan3-700an.As you now spartan3-an series have internal flash.when I am going to program FPGA only in Impact some times it is not programmed and I have a message that "Done pin did not go high" in this time when I am going to program internal flash I have this message "error shows in the status register, CRC Error Bit is NOT 0".these errors appear some times not every time.

Can you help me about this problem

thanks

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Xilinx Employee
Xilinx Employee
517 Views
Registered: ‎06-06-2018

Hi @ebi1359,

CRC errors are typically due to clocking or SI issues on the board.
If a CRC error occurs, try slowing down the configuration speed(try reducing it to 3MHz or below), or investigating the SI characteristics of the configuration signals (in particular, the clock line).

Refer this AR#24024, for more information and how to debug the issue through Status Register values.

 

Regards,

Deepak D N

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Deepak D N
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Moderator
Moderator
508 Views
Registered: ‎01-15-2008

can you provide the log file for the both the scenarios

can you check mode pins and VS pins are set according to the requirement for ISF configuration mentioned in UG332

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Visitor
Visitor
492 Views
Registered: ‎07-01-2018

my mode pins are in correct state(0,1,1 for internal flash) but my vs pins are connected to I/O's without pull up or pull down.

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Moderator
Moderator
486 Views
Registered: ‎01-15-2008

ok, variant select pins should be either 101 or 111 as mentioned in table 10-2 during configuration. other condtions will be invalid and this might be the cause of inconsistent behaviour since you dont have any pullups or pulldown for VS pins

https://www.xilinx.com/support/documentation/user_guides/ug332.pdf

 

 

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Visitor
Visitor
458 Views
Registered: ‎07-01-2018

can I solve this problem without changing in my hardware and change the board?

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Moderator
Moderator
453 Views
Registered: ‎01-15-2008

check page 219 from the following link where it states that VS pins have weak pull-ups but it is recommended to have external resistors.

https://www.xilinx.com/support/documentation/user_guides/ug332.pdf

Variant select pins are dual purpose so there shouldn't be any activity from peripherls on this IO's if used until the configuration is complete if in case you are depending on the weak internal pull-ups. 

However, it is suggested to follow the recommendations for the VS pins to have a correct configuration.

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