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DiamondBound
Observer
Observer
450 Views
Registered: ‎03-18-2020

synthesis define

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What is the procedure to set a define that is only used in synthesis not simulation? Does vivado provide any defines that are true during synthesis?

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DiamondBound
Observer
Observer
385 Views
Registered: ‎03-18-2020
I solved my problem by using `ifndef SIM_ONLY as a header in my top module of the FPGA.
For example:
// channel builds are used to test an individual channel or a group to speed up simulation
`ifndef SIM_ONLY
`define CHANNEL0_BUILD 1
`define CHANNEL1_BUILD 1
`define CHANNEL2_BUILD 1
`define CHANNEL3_BUILD 1
`else

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yangc
Xilinx Employee
Xilinx Employee
411 Views
Registered: ‎02-27-2019

Could you provide more details about your request? The source file can be set "synthesis" "implementation" "simulation" like below:

Capture.PNG

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DiamondBound
Observer
Observer
386 Views
Registered: ‎03-18-2020
I solved my problem by using `ifndef SIM_ONLY as a header in my top module of the FPGA.
For example:
// channel builds are used to test an individual channel or a group to speed up simulation
`ifndef SIM_ONLY
`define CHANNEL0_BUILD 1
`define CHANNEL1_BUILD 1
`define CHANNEL2_BUILD 1
`define CHANNEL3_BUILD 1
`else

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yangc
Xilinx Employee
Xilinx Employee
382 Views
Registered: ‎02-27-2019

Please set your post as an accepted solution, then others may refer to it.

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